FPGA Out-of-Band Bridging With Shared Buffering for Servers
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Solution Overview
Problem
Existing out-of-band bridging systems in SoC array servers face challenges with high costs, complex design, and limited data transmission capabilities due to the exponential increase in peripheral devices and buffering requirements as the number of computing units increases, particularly for UART and USB interfaces.
Innovation Solution
A field-programmable gate array (FPGA) structure with multiple data interface modules and a buffer module that facilitates data transmission between in-band and out-of-band interfaces, reducing the need for external chips and simplifying design by using internal buffering and switching functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of computing units increases to achieve high density, then server performance and integration capability improve, but the number of peripheral devices and buffering requirements increase exponentially, leading to higher costs and more complex design
Solution Approach 1:
The patent combines multiple data interface modules (first data interface modules for in-band interfaces and second data interface modules for out-of-band interfaces) and buffer modules into a single integrated FPGA structure. This merging eliminates the need for separate external chips for each interface, reducing the overall number of peripheral devices while maintaining the ability to handle multiple computing units simultaneously.
Solution Approach 2:
The FPGA structure is designed with multi-functional data interface modules that can handle various interface types (IIC, UART, USB) through a unified architecture. The buffer module serves multiple purposes by buffering data from different interface types and routing it to appropriate destinations, making the system universal and adaptable to different computing unit configurations without requiring interface-specific external chips.
2Adaptability or versatility
If multiple external chips are used to support various interface types, then interface compatibility improves, but system cost and device count increase
Solution Approach 1:
The patent integrates support for multiple interface types (IIC, UART, USB) within the FPGA structure itself, combining what would traditionally require separate external chips into a single unified device. The first data interface modules and second data interface modules are consolidated within the FPGA, eliminating the need for multiple peripheral chips while maintaining full interface compatibility.
Solution Approach 2:
The FPGA structure employs universal data interface modules that can operate with multiple interface types through configuration rather than requiring dedicated hardware for each interface. This multi-functionality allows a single peripheral device (the FPGA) to replace multiple interface-specific chips, reducing the quantity of peripheral devices while preserving adaptability across different interface standards.
3Productivity
If chip stacking is used to handle multiple interfaces, then data transmission capability improves, but design complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges multiple interface handling capabilities into a single FPGA structure with integrated buffer modules, eliminating the need for chip stacking architectures. All data transmission functions for multiple interfaces are consolidated within one device, simplifying the manufacturing process by removing the complex alignment and integration requirements associated with stacking multiple chips.
4Reliability
If more buffer modules are added to handle increased data traffic, then data transmission quality improves, but device complexity and cost increase
Solution Approach 1:
The patent combines buffering functions for multiple interface types into unified buffer modules within the FPGA structure. Rather than adding separate buffer chips for each interface, the integrated buffer modules handle data from all interfaces centrally, maintaining data transmission quality while avoiding the exponential increase in complexity that would result from proliferating individual buffer components.
Data Source
AI summary
Provided are a field-programmable gate array structure for implementing out-of-band bridging, an out-of-band bridging system and method, and a server, relating to the field of computer technology, especially a server. The field-programmable gate array structure includes at least two first data interface modules, at least two second data interface modules, and a buffer module. Each first data interface module is matched to a respective in-band data interface module. Each second data interface module is matched to a respective management data interface module. The buffer module is configured to buffer data of the first data interface modules and data of the second data interface modules. Each second data interface module is configured to perform data transmission with at least two first data interface modules through the buffer module.