FPGA Logic Cell Architecture Using WLUT Chains and Buddy Logic
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Solution Overview
Problem
Existing Field Programmable Gate Array (FPGA) logic cells are not area and timing efficient, and their placement is not optimal for implementing complex digital logic circuits.
Innovation Solution
The design introduces a new logic cell structure that forms a Wide Look-Up Table (WLUT) chain and buddy logic, utilizing multiplexers to enhance signal processing and reduce the number of logic cells required, allowing for more efficient area usage and faster performance by replacing traditional LUTs with multiplexed chains and dedicated links between cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional LUT-based logic cells are used, then the logic cell structure is simple and easy to manufacture, but the area usage is inefficient and timing performance is poor
Solution Approach 1:
The patent merges multiple LUTs into a single logic cell to form a WLUT chain structure. Specifically, multiple LUTs are combined within one logic cell boundary, allowing them to share resources and reduce the total number of logic cells needed. This merging approach improves area efficiency while maintaining the functional capabilities of individual LUTs.
Solution Approach 2:
The logic cell is designed with multi-functional capabilities through the inclusion of multiplexers that can route signals between different LUTs and external inputs/outputs. The same logic cell structure can implement various logic functions by configuring the multiplexers and LUTs differently, providing universality without requiring multiple specialized cell types.
2Adaptability or versatility
If more logic cells are used to implement complex functions, then the functional capability is improved, but the area usage becomes inefficient
Solution Approach 1:
Multiple LUTs are merged into a single logic cell to form a WLUT chain, reducing the total number of logic cells required to implement complex functions. This merging allows shared resources and reduces area overhead while maintaining full functional capability of each LUT within the chain.
Solution Approach 2:
The patent introduces a chain structure dimension to the traditional LUT organization. Instead of using separate logic cells for each LUT, LUTs are arranged in chains within logic cells, creating a hierarchical structure that reduces area usage while preserving functional versatility through the chain connections.
3Ease of operation
If traditional logic cell interconnection is used, then the placement is straightforward, but the timing efficiency and placement flexibility are limited
Solution Approach 1:
The logic cell is segmented into distinct functional blocks including multiple LUTs, multiplexers, and input/output terminals. This segmentation allows independent optimization of each block while maintaining overall placement simplicity. The modular segmented structure enables better timing optimization without complicating the placement process.
Solution Approach 2:
The logic cell incorporates dynamic signal routing through multiplexers that can be configured to connect different LUTs and inputs/outputs based on the required function. This dynamic configurability allows the same physical structure to adapt to different timing requirements and placement scenarios, improving both timing efficiency and placement flexibility.
Data Source
AI summary
The present invention provides integrated circuits with improved logic cells. In one embodiment, an integrated circuit having a plurality of logic cells (LC) is provided, each LC comprising: a lookup table having a LUT output terminal; and, a first multiplexer; wherein, a first multiplexer input terminal is connected to of a first input terminal of the LC, a second multiplexer input terminal is connected to the LUT output terminal, a multiplexer output terminal is connected to a first output terminal of the LC, and a multiplexer select terminal is connected to a second input terminal of the LC so as to select which of the signals appearing at the first and second multiplexer input terminal to pass through; wherein, by coupling in chain the first input terminal of one LC to the first output terminal of another LC, a WLUT chain is formed.