FPGA Configuration Buffer ECC for SEU Resilience
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Solution Overview
Problem
FPGA chips are prone to single event upsets (SEU) due to external factors like power supply, radiation, and particle impact, leading to errors in configuration content and circuit function, necessitating improved reliability of configuration content in high-reliability applications.
Innovation Solution
An FPGA design that reuses a buffer memory with an error correcting code (ECC) check function, where configuration bitstreams are written in units of configuration chains, and the key configuration chain is periodically updated using a control circuit and timer, ensuring accurate storage and correction of errors in the configuration memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If configuration bitstreams are stored in configuration memory without error correction, then storage speed is improved, but reliability deteriorates due to SEU errors from external factors
Solution Approach 1:
The configuration buffer is designed to serve dual purposes: it acts as a temporary storage buffer during configuration bitstream loading, and simultaneously functions as an error correction storage for key configuration chains during runtime. The buffer includes ECC check functionality and can store both full configuration chains and corrected key configuration chains, eliminating the need for separate error correction memory structures.
2Reliability
If configuration memory is periodically updated to correct SEU errors, then reliability is improved, but running time increases due to update operations
Solution Approach 1:
The configuration buffer pre-caches the complete configuration bitstream during the loading phase before the FPGA begins normal operation. This preliminary action ensures that when SEU errors occur during runtime, the corrected key configuration chains can be quickly retrieved from the already-loaded buffer without requiring time-consuming re-loading operations, thus minimizing impact on running time.
Solution Approach 2:
The control circuit periodically reads the key configuration chain from the configuration buffer and updates the configuration memory at predetermined time intervals. This periodic update mechanism ensures that SEU errors are corrected in a timely manner without requiring continuous monitoring, balancing reliability improvement with minimal disruption to normal operation.
3Reliability
If key configuration chain is cached in configuration buffer, then error correction capability is improved, but memory resource utilization deteriorates
Solution Approach 1:
The system identifies and prioritizes protection of the key configuration chain, which contains the most critical configuration data. Instead of applying error correction to the entire configuration bitstream, the invention focuses ECC resources specifically on caching and protecting the key configuration chain in the configuration buffer, optimizing the balance between reliability improvement and memory resource consumption.
Data Source
AI summary
A field programmable gate array (FPGA) for improving the reliability of a key configuration bitstream by reusing a buffer memory includes a configuration buffer, a configuration memory and a control circuit. The configuration memory includes N configuration blocks. The FPGA stores a key configuration chain by using the configuration buffer and ensures correct content of the key configuration chain through an error correcting code (ECC) check function of the configuration buffer, so that when the FPGA runs normally, a control circuit reads the key configuration chain in the configuration buffer at an interval of a predetermined time and writes the key configuration chain into a corresponding configuration block to update the key configuration chain, thereby ensuring accuracy of the content of the key configuration chain and improving running reliability of the FPGA.