FPGA Memory Buffer Partitioning for Multiple Bit Upset Correction
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Solution Overview
Problem
Existing methods for detecting and correcting multiple bit upsets in field programmable gate arrays (FPGAs) are inefficient, requiring excessive hardware and slowing down system performance due to the need for complex algorithms and triplication of components, which is particularly problematic in harsh environments like space where radiation can cause transient errors.
Innovation Solution
A method that partitions a memory buffer into portions to store original and modified data, allowing for efficient comparison and correction of bit errors by calculating and comparing parity bits, thereby reducing hardware requirements and improving detection and correction speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If triplicated-redundant information storage or complex EDAC schemes are used to correct multiple bit upsets, then error correction capability is improved, but device complexity and processing time increase
Solution Approach 1:
The memory buffer is segmented into multiple portions, with each portion storing a different version of the data (original, modified, inverted). This segmentation allows the system to detect and correct multiple bit upsets by comparing different segments without requiring full triplication of the entire memory system, thereby reducing hardware complexity while maintaining error correction capability.
Solution Approach 2:
The patent applies inversion by storing not only the original data but also modified and inverted versions of the data in different portions of the memory buffer. By comparing the inverted version with the original, the system can detect bit upsets that would be missed by traditional single-version storage, improving reliability without proportionally increasing hardware complexity.
2Measurement precision
If complex algorithms and triplication of components are used to detect and correct multiple bit upsets, then error detection accuracy is improved, but processing speed deteriorates
Solution Approach 1:
The system performs preliminary actions by pre-storing multiple versions of the data (original, modified, inverted) in the memory buffer before error detection is needed. When a bit upset occurs, the pre-stored versions are already available for immediate comparison, eliminating the need for complex real-time calculations and thereby maintaining high processing speed while achieving accurate error detection.
3Reliability
If triplication of storage memory is used to correct multiple bit upsets, then error correction capability is improved, but hardware resources increase
Solution Approach 1:
Instead of triplicating the entire storage memory, the patent segments the memory buffer into multiple portions and stores different versions of the data in each segment. This approach achieves error correction capability comparable to triplication but uses fewer hardware resources by avoiding redundant storage of complete data copies across the entire memory system.
Data Source
AI summary
A method for detecting and correcting bit errors. The method includes the steps of receiving original data, partitioning the memory storage into a first portion and a second portion, storing the original data in the first portion of the memory buffer, modifying the original data into modified data, storing the modified data in the second portion of the memory buffer, comparing the original data with the modified data, combining the original data and the modified data to create a final data stream, and outputting the final data stream. The method may further include the step of calculating and storing parity data.