FPGA Cache Bypass for Host Memory Coherence
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Solution Overview
Problem
Field-programmable gate arrays (FPGAs) lack support for shared memory, leading to costly delays in testing shared memory features like cache coherence, as they cannot model or evaluate shared memory effectively due to serial message-passing architectures not supporting this functionality.
Innovation Solution
A method is implemented where a cacheability status is assigned to pages in the memory of a host computer connected to an FPGA, allowing instructions to bypass FPGA caches when accessing non-cacheable pages, enabling coherent shared access to host computer memory through programmed I/O transactions and software virtualization techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA uses serial message-passing architecture to connect to host computer, then communication interface compatibility is improved, but shared memory support is lost
Solution Approach 1:
The patent introduces a cacheability status mechanism as an intermediary layer between the FPGA and host computer memory. This mediator enables the FPGA to distinguish between cacheable and non-cacheable memory regions, effectively implementing shared memory semantics over the serial PCI-e interface. The cacheability status acts as a control signal that mediates the interaction between FPGA caches and host memory, resolving the contradiction between interface compatibility and shared memory support.
2Speed
If FPGA caches are used for memory access, then access speed is improved, but cache coherence cannot be maintained
Solution Approach 1:
The patent applies local quality by differentiating memory access behavior based on cacheability status. Non-cacheable pages are accessed directly without caching, maintaining coherence with host memory. Cacheable pages utilize FPGA caches for accelerated access. This localized differentiation of access modes allows the system to optimize for speed where coherence is not required while maintaining coherence where needed, resolving the contradiction between access speed and cache coherence.
3Device complexity
If shared memory testing is deferred until hardware implementation, then FPGA prototyping simplicity is maintained, but testing delays and costs increase
Solution Approach 1:
The patent implements preliminary action by enabling shared memory testing capabilities during the FPGA prototyping phase itself, rather than deferring to hardware implementation. The cacheability status mechanism is configured in software before hardware fabrication, allowing shared memory behavior to be tested and validated early in the development cycle. This preliminary testing action prevents costly delays and redesigns later in the process.
Data Source
AI summary
A method may include assigning a cacheability status to a page. The page may be in a memory of a host computer communicatively connected to a processor core on a field-programmable gate array (FPGA). The FPGA may include one or more caches. The method may further include obtaining an instruction including a reference to the page, determining, based on the cacheability status, whether the page is non-cacheable, and resolving the reference to the page, based on determining that the page is non-cacheable, bypassing the one or more caches of the FPGA.