FPGA Cache Coherency for Bandwidth-Constrained Data Transfer
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Solution Overview
Problem
In information processing systems, the exchange of data between multiple arithmetic circuits via a shared memory can lead to memory bandwidth consumption, degrading system performance due to cache limitations and data replacement in FPGA caches.
Innovation Solution
The implementation of a transmitting circuit and a receiving circuit that manage cache memory to restrict access, ensuring data transfer between FPGA arithmetic circuits occurs without purging data from the cache, thereby reducing memory bandwidth consumption by using cache coherency protocols to maintain data consistency and secure transfer areas in the cache.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If arithmetic circuits exchange data via shared memory, then data transfer between circuits is enabled, but memory bandwidth is consumed and system performance degrades
Solution Approach 1:
The patent introduces cache memories as intermediary storage between arithmetic circuits and main memory. The cache controller acts as a mediator that manages data transfer between caches and main memory, enabling arithmetic circuits to exchange data through cache coherence protocols without directly consuming main memory bandwidth for every transfer operation.
Solution Approach 2:
The memory hierarchy is segmented into multiple levels: cache memories associated with individual arithmetic circuits and a main memory. This segmentation allows data to be stored and exchanged at the cache level for frequently accessed data, reducing the need for main memory accesses and thereby reducing overall memory bandwidth consumption.
2Speed
If cache memories are used for data exchange, then transfer speed is improved, but cache data may be purged due to capacity limitations
Solution Approach 1:
The cache coherence protocol implements feedback mechanisms where cache controllers monitor and communicate the state of cached data. When data is modified in one cache, the coherence protocol provides feedback to other caches and the main memory, ensuring that data is not purged inadvertently and maintaining data integrity across the system.
Solution Approach 2:
The system performs preliminary actions by allocating specific cache regions for inter-circuit data exchange and establishing coherence protocols before data transfer begins. This preliminary setup ensures that cache data is protected from being purged during the transfer process, maintaining reliability while enabling high-speed transfer.
3Productivity
If multiple arithmetic circuits access shared memory simultaneously, then processing parallelism is achieved, but memory bandwidth contention increases
Solution Approach 1:
Each arithmetic circuit is assigned its own dedicated cache memory, segmenting the memory access path. This allows multiple arithmetic circuits to operate in parallel with minimal contention, as they can access their local caches independently without competing for the same memory bandwidth resources.
Solution Approach 2:
Cache controllers serve as intermediaries that manage access between arithmetic circuits and the main memory. They coordinate simultaneous access requests from multiple circuits, allowing parallel processing to proceed efficiently while minimizing actual contention for the shared memory bandwidth through intelligent request management and timing.
Data Source
AI summary
An information processing device includes a first package including a first arithmetic circuit, first cache memory and a transmitting circuit, as well as a second package including a second arithmetic circuit, second cache memory and a receiving circuit. The first arithmetic circuit is configured to provide transfer data to the first cache memory that is destined for the second cache memory. The transmitting circuit is configured to transmit to the receiving circuit an indication of a data transfer of the transfer data and to restrict use of the first cache memory for data other than the transfer data during the data transfer. The receiving circuit is configured to receive the indication of the data transfer, to acquire the transfer data stored in the first cache memory and to store the acquired transfer data in the second cache memory.