FPGA Cache-Line Snapshotting for Power-Failure Recovery
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Solution Overview
Problem
Current methods for saving application states during power failures are inefficient, leading to high latency and throughput penalties, and are not suitable for highly intensive in-memory computing jobs, requiring expensive application rewrites or inefficient data passing through the operating system kernel.
Innovation Solution
An FPGA is used to snoop a cache coherent interconnect for dirty cache lines, writing data or their addresses to a non-volatile memory based on buffer size and snooping frequency, enabling efficient snapshotting at the level of single cache lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional persistent storage (hard drives, SSDs) is used for taking snapshots, then data can be saved persistently, but latency and throughput penalties increase and memory page size granularity limits recovery speed
Solution Approach 1:
The patent segments the memory snapshot process into cache line-level granularity instead of traditional page-level or full memory dumps. By monitoring and capturing individual cache lines that contain dirty data, the system achieves fine-grained persistent storage with minimal impact on performance, as only modified portions are written to non-volatile memory.
Solution Approach 2:
The patent introduces a new dimension of operation by having the FPGA directly access the memory controller and cache coherent interconnect, bypassing the traditional OS kernel file system path. This dimensional shift from software-mediated access to hardware-level direct access eliminates overhead and enables sub-page granularity snapshotting.
2Reliability
If NVM is used to store application state directly, then persistence is achieved, but new APIs are required and application rewrite is expensive
Solution Approach 1:
The patent introduces an intermediary layer - the FPGA - that sits between the existing application and the NVM storage. This intermediary transparently captures cache line data and handles all NVM operations, allowing applications to continue using existing memory access patterns without requiring new APIs or code modifications.
Solution Approach 2:
The patent creates copies of dirty cache lines in the FPGA's buffer before writing to NVM. This copying mechanism allows the original application memory to remain unchanged while maintaining persistent copies elsewhere, enabling persistence without application awareness or modification.
3Reliability
If NVM is used with file systems or disk partitions, then persistence is achieved, but data must pass through the operating system kernel which is highly inefficient
Solution Approach 1:
The patent extracts the data persistence function from the OS kernel file system layer and implements it directly in hardware at the FPGA level. By taking out the kernel mediation step and replacing it with direct hardware access to the cache coherent interconnect, the system achieves persistence without the efficiency penalties of software-based file systems.
4Reliability
If capacitor-based power backup is used, then application state can be saved during power failure, but the system is not aware of memory boundaries and saves entire memory content
Solution Approach 1:
The patent applies local quality by having different parts of the memory system treated differently - only the dirty cache lines that contain modified data are captured and persisted, while clean cache lines are left unchanged. This localized approach to data capture dramatically reduces the quantity of data that needs to be written during power failure events.
Solution Approach 2:
The patent performs preliminary action by continuously monitoring and buffering dirty cache lines in the FPGA before power failure occurs. This preliminary capture of modified data means that when power is lost, only the pre-identified dirty data needs to be written to NVM, rather than dumping entire memory pages or contents.
Data Source
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AI summary
There is provided mechanisms for snapshotting data of a host application. A method is performed by an FPGA. The method comprises snooping a cache coherent interconnect of a host computer on which the host application is running. The cache coherent interconnect is snooped for dirty cache lines, each dirty cache line having an address. The method comprises writing, only when the address of any of the dirty cache lines has a match in a snapshot address table, data of that dirty cache line to a non-volatile memory.