FPGA Cache Line Tracking via Coherence Interconnect Monitoring
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current systems tracking modified data in computing systems at the page level are inefficient, especially when only a small part of a page is modified, as they require writing back the entire page to persistent storage.
Innovation Solution
Implementing a method to track dirty cache lines by monitoring cache coherence events on a coherence interconnect and using a field programmable gate array (FPGA) to add a representation of cache lines to a buffer, allowing for efficient tracking of dirty cache lines instead of pages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If page level tracking is used to track modified data, then the tracking mechanism is simple and manageable, but the efficiency deteriorates when only a small part of a page is modified as the entire page must be written back
Solution Approach 1:
The patent segments the page-level tracking granularity into cache line-level tracking. Instead of tracking entire pages as the minimum unit, the system divides pages into smaller cache line units and tracks dirty status at this finer granularity. This allows only the specific cache lines that are modified to be identified and written back, rather than writing back entire pages, thus eliminating unnecessary data transfer while maintaining efficient tracking through buffer-based management of dirty cache line addresses.
2Loss of substance
If cache line level tracking is implemented, then the data transfer efficiency is improved by tracking only modified cache lines, but the device complexity increases due to the need for monitoring coherence events
Solution Approach 1:
The system employs self-service by utilizing the existing cache coherence event generation mechanism to automatically provide the information needed for tracking. When cache lines are modified, the hardware naturally generates coherence events that are monitored by the buffer, which then automatically records the dirty cache line addresses without requiring additional complex monitoring infrastructure. This approach leverages existing system behavior to simplify the tracking implementation.
Solution Approach 2:
The patent introduces a buffer as an intermediary component between the cache coherence mechanism and the dirty page tracking system. This buffer serves as a mediation layer that receives coherence events, processes them to identify dirty cache lines, and manages the tracking information. By inserting this intermediary, the system achieves fine-grained cache line tracking without directly complicating the core cache coherence hardware, as the buffer absorbs the complexity of event monitoring and address management.
3Ease of manufacture
If entire pages are written back to persistent storage, then the implementation is straightforward, but the time consumption increases unnecessarily
Solution Approach 1:
The patent applies partial action by writing back only the necessary portion of data - specifically, only the dirty cache lines that have been modified - rather than writing back the entire page. The buffer tracks which cache lines within a page are dirty, and the write-back operation is performed selectively on only those specific cache lines. This partial approach significantly reduces write-back time by avoiding the transfer of clean data that doesn't need to be persisted, while the implementation remains relatively simple through the use of buffer-based tracking.
Data Source
AI summary
A device is connected via a coherence interconnect to a CPU with a cache. The device monitors cache coherence events via the coherence interconnect, where the cache coherence events relate to the cache of the CPU. The device also includes a buffer that can contain representations, such as addresses, of cache lines. If a coherence event occurs on the coherence interconnect indicating that a cache line in the CPU's cache is dirty, then the device is configured to add an entry to the buffer to record the dirty cache line.