FPGA Cache Prefetching for Memory Access Latency
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Solution Overview
Problem
Memory access latency is high due to CPU-intensive processes in accessing structured data sets, and tiered memory controllers outside the coherency domain lack direct access to coherency information, making disaggregated memory tiering architectures less practical.
Innovation Solution
A programmable logic device, such as an FPGA, is placed on the memory bus to snoop on CPU requests and prefill a cache with data based on memory access patterns, reducing latency by predicting subsequent accesses and keeping the cache warm, thereby improving device throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the CPU accesses structured data sets directly from memory, then data retrieval is performed, but memory access latency is high and CPU resources are consumed
Solution Approach 1:
The patent implements a hardware cache that pre-loads and stores frequently accessed structured data sets before the CPU needs them. The cache controller monitors memory access patterns and proactively retrieves data from main memory into the hardware cache, so that when the CPU requests data, it is already available in the faster cache memory, thereby reducing memory access latency and freeing CPU resources for computation.
Solution Approach 2:
The patent introduces a hardware cache as an intermediary component between the CPU and main memory. This cache layer acts as a buffer that stores copies of frequently accessed data, allowing the CPU to access data from the fast cache rather than directly from slow main memory. The cache controller manages this intermediary layer, handling data retrieval and storage operations independently of the CPU.
2Adaptability or versatility
If tiered memory controllers are placed outside the coherency domain, then memory pooling and tiering are enabled, but direct access to coherency information is lost
Solution Approach 1:
The patent introduces a cache controller as an intermediary component that sits between the tiered memory controllers outside the coherency domain and the CPU within the coherency domain. This controller maintains coherency information and provides direct access to it, enabling the system to benefit from both memory tiering capabilities and coherency information access. The controller translates and manages memory operations while preserving coherency relationships.
Solution Approach 2:
The patent segments the memory system into distinct functional components: tiered memory controllers outside the coherency domain for pooling and tiering operations, and a cache controller within the coherency domain for maintaining and accessing coherency information. This segmentation allows each component to perform its specialized function while working together through defined interfaces, resolving the contradiction between memory tiering and coherency access.
Data Source
AI summary
Circuitry, systems, and methods are provided for an integrated circuit device including a memory storing a data structure, a cache storing a portion of the structure data, and an acceleration function unit providing hardware acceleration for a host device. The acceleration function unit may provide the hardware acceleration by intercepting a request from the host device to access the memory, where the request comprises an address corresponding to a data node of the data structure, identifying a next data node based at least in part on decoding the data node, and loading the next data node into the cache for access by the host device.