FPGA Carry Chain Conversion for Critical Path Delay Reduction
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Solution Overview
Problem
The existing FPGA chip synthesis process experiences significant time delays due to the use of look-up tables (LUTs) in implementing logic functions, necessitating an optimization method for the FPGA carry chain to enhance performance and reduce timing delays.
Innovation Solution
A method is introduced where a logic synthesis tool identifies critical paths in the synthesis netlist and converts look-up tables with fewer actual inputs and adjacent to carry chains into carry chains, reducing delays and improving circuit frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If look-up tables are used to implement logic functions in FPGA, then logic functions can be implemented with standard components, but large time delay is generated in the critical path
Solution Approach 1:
The patent changes the structural parameters of the logic implementation by converting LUTs to carry chain structures in the critical path. This parameter change transforms the implementation from a general-purpose LUT-based approach to a specialized carry-chain approach, reducing the internal transmission delay from multiple LUT stages to a single carry chain stage, thereby resolving the time delay issue while maintaining logic function implementation capability
2Speed
If look-up tables are converted to carry chains in the critical path, then time delay is reduced and maximum frequency is increased, but device complexity increases due to selective conversion requirements
Solution Approach 1:
The patent applies local quality by selectively converting only those LUTs that lie on the critical path to carry chain structures, while leaving other LUTs unchanged. This localized transformation optimizes the specific region causing performance bottlenecks (the critical path) without unnecessarily complicating the entire circuit, thereby increasing maximum frequency while controlling device complexity
Data Source
AI summary
Provided are a method for optimizing a circuit structure based on an FPGA carry chain, a computer device and a non-transitory computer-readable storage medium, in which logic synthesis is performed, by a logic synthesis tool, on a target logic operation, and a synthesis netlist is obtained through the logic synthesis; a critical path is obtained in the synthesis netlist; and in response to the number of actual inputs of a look-up table in the critical path being not greater than a preset threshold, and at least one of elements adjacent to two ends of a reference path in the critical path being a carry chain, the look-up table in the critical path is converted into a carry chain, where the reference path includes the look-up table, and only one look-up table or multiple adjacent look-up tables compose the reference path.