FPGA Carry Chain Packing for Logic Utilization

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Solution Overview

Problem

Current electronic design automation (EDA) tools face challenges in efficiently packing adders on field programmable gate arrays (FPGAs) for low precision multipliers, leading to low logic utilization and prolonged design compilation times.

Innovation Solution

The method involves using continuous carry chains to map multiple logical adders onto a single logical adder, optimizing the placement and routing of arithmetic functions by selecting a carry chain length supported by the target device's resources and designating bit positions to prevent overflow, thereby increasing logic utilization and reducing compilation time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple logical adders are mapped onto a single logical adder using continuous carry chains, then logic utilization is improved, but device complexity increases

Engineering Contradiction:

Improvelogic utilizationVSAvoidadder packing complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

Multiple logical adders are merged onto a single logical adder resource by utilizing continuous carry chains. The patent maps several adder operations to share a common carry chain infrastructure, allowing multiple logical adders to be implemented using fewer physical adder resources, thereby improving logic utilization on the FPGA device.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The continuous carry chain is designed to serve multiple functions by supporting various adder configurations and operations. The same carry chain infrastructure can be used for different adder widths and arrangements, making the resource universal and adaptable to different multiplier designs while maintaining high utilization.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If adders are efficiently packed using continuous carry chains, then logic utilization is improved, but compilation time increases

Engineering Contradiction:

Improvelogic utilizationVSAvoidcompilation time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The EDA tool performs preliminary analysis and identification of continuous carry chain opportunities during the synthesis stage. By detecting potential carry chain configurations early in the design process and preparing the mapping in advance, the tool optimizes adder packing before placement, reducing the computational burden during later compilation stages.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The synthesis tool automatically identifies and exploits continuous carry chain opportunities without requiring manual intervention or complex iterative optimization during placement. The tool self-services by detecting patterns in the netlist that can utilize carry chains and automatically mapping adders accordingly, streamlining the compilation process.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS11216249B2Method and apparatus for performing field programmable gate array packing with continuous carry chains

Publication Date: 2022.01.04 ALTERA CORP

AI summary

A method for designing a system on a target device includes identifying a length for a carry chain that is supported by predefined quanta of a resource on the target device. A plurality of logical adders is mapped onto a single logical adder implemented on the carry chain subject to the identified length to increase logic utilization in a design for the system.