FPGA Carry Chain Switching for Low Leakage and Fast Addition
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional FPGA carry chains consume excessive power and exhibit latency due to ripple-based designs, leading to performance degradation and power drain from leakage currents, even when not actively used.
Innovation Solution
The implementation of a carry bit generating chain with independent logic units that can be selectively empowered or depowered, reducing leakage current and operating in parallel with sum bit generation, allowing direct operation on input data without serial dependency on latent results from other logic blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional ripple carry adder design is used, then device complexity is reduced, but speed deteriorates due to serial dependency of carry bits
Solution Approach 1:
The carry chain is segmented into independent logic units, each capable of generating carry bits independently. This segmentation allows parallel operation of carry generation across multiple stages, eliminating the serial dependency inherent in ripple carry adders while maintaining structural simplicity.
Solution Approach 2:
Carry bits are generated in advance by dedicated carry logic units before the addition operation is fully completed. This preliminary generation of carry bits allows the sum calculation to proceed without waiting for carry propagation, significantly improving addition speed.
2Speed
If conventional carry logic is always active, then speed is maintained, but power consumption increases due to leakage current
Solution Approach 1:
The carry logic units are designed to be dynamically controllable, allowing them to be switched between active and inactive states. This dynamic control enables the system to maintain high speed performance when carry operations are needed while minimizing power consumption when they are not, by disabling leakage current through control signals.
Solution Approach 2:
The carry logic units operate periodically rather than continuously, being activated only when addition or subtraction operations are performed. This periodic operation eliminates continuous leakage current while maintaining operational speed, as the units are re-enabled quickly when needed.
3Speed
If carry look-ahead block is used, then speed is improved, but device complexity and power consumption increase
Solution Approach 1:
Instead of using a centralized carry look-ahead block, the carry generation function is segmented and distributed to individual logic units. Each unit independently generates carry bits using simplified logic, achieving fast carry propagation without the complexity of a centralized look-ahead structure.
Solution Approach 2:
The carry generation function is extracted from the main addition logic and implemented as separate, dedicated carry logic units. This extraction allows carry bits to be generated independently and in parallel, improving speed while keeping each individual unit simple and low-power.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces power consumption by disabling leakage currents when not in use and enhances performance by enabling parallel carry bit generation, thereby improving the efficiency and speed of addition/subtraction operations in FPGAs.
Implementation Method 1
a switching transistor connected to the ground sink terminal of the carry logic unit, where the switching transistor is structured and interposed so as to support flow of the unit empowering current through the respective carry bit generating logic unit
Data Source
AI summary
An in-FPGA carry chain is provided that does not exhibit significant leakage current. In particular, parts of the carry chain can be switched on/off when desired. In this manner, carry chain parts can have their leakage currents substantially disabled when they are not in use, thus saving power. Additionally, there is provided a carry chain whose logic is separate from the other parts (e.g., LUTs) of the logic blocks that perform the remaining arithmetic functions, and whose inputs are the input data to be added, rather than data that is output in delayed fashion from the other parts (e.g., LUTs) of the logic blocks. Such a configuration reduces latency by allowing the carry chain to operate directly on the received input data without need to wait on results from the other parts (e.g., LUTs) of the logic blocks.