FPGA Arithmetic Circuit Diversity for Common-Cause Error Detection
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Solution Overview
Problem
Conventional error verification methods in programmable logic devices, such as FPGAs, fail to detect errors caused by common factors like temperature, voltage, and clock fluctuations due to redundant arithmetic operation circuits producing the same results even when errors occur, resulting in a low error detection rate.
Innovation Solution
A programmable logic device that forms multiple arithmetic operation circuits with different combinations and connection states of circuit blocks, allowing for error detection by comparing their output results through a verification circuit, thereby improving the error detection rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant arithmetic operation circuits with the same circuit block combination are used for error verification, then the verification capability is provided, but the error detection rate is low because common factors cause the same errors in all circuits
Solution Approach 1:
The patent applies local quality by making each arithmetic operation circuit have a different combination of circuit blocks while maintaining the same overall arithmetic function. Specifically, the first arithmetic operation circuit uses a first combination of circuit blocks and the second arithmetic operation circuit uses a second combination different from the first, creating local variations in circuit structure that cause different error patterns under common factors, thereby improving error detection capability.
Solution Approach 2:
The patent segments the arithmetic operation function into multiple different circuit block combinations. Instead of using identical redundant circuits, the arithmetic operation is divided into multiple pathways with different circuit configurations, allowing errors caused by common factors to manifest differently in each segment, enabling detection through comparison of results.
2Adaptability or versatility
If the number of circuit blocks is increased to perform more arithmetic operations, then the arithmetic operation capability is improved, but the probability of malfunction due to charged particles increases
Solution Approach 1:
The patent implements feedback by comparing the arithmetic operation results from the first arithmetic operation circuit and the second arithmetic operation circuit. The verification circuit receives results from both circuits and determines whether they match, providing feedback that indicates whether an error has occurred. This allows the system to detect malfunctions caused by charged particles even as the number of circuit blocks increases.
3Reliability
If multiple arithmetic operation circuits are provided for error verification, then the verification function is achieved, but the circuits produce the same results even when errors occur due to common factors
Solution Approach 1:
The patent applies asymmetry by creating asymmetric circuit configurations where the first arithmetic operation circuit and the second arithmetic operation circuit have different combinations of circuit blocks. This asymmetry ensures that when common factors affect the circuits, they produce different error patterns rather than identical results, allowing the verification circuit to detect errors through result comparison.
Data Source
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AI summary
Arithmetic operation circuits (L1 to L3) and a verification circuit (21) are formed by loading configuration information into a configuration memory in an FPGA (10). Arithmetic operation circuits (L1 to L3) have the same arithmetic operation function, but are different from each other in combination of the circuit blocks. The arithmetic operation circuits (L1, L3) are formed by combining the circuit blocks to make the maximum use of the DSP block (12), while the arithmetic operation circuit (L2) is formed by combining the circuit blocks other than DSP block (12). The arithmetic operation circuits (L1, L2) each are configured to use a block RAM (13) as the data hold memory, while the arithmetic operation circuit (L3) is configured to use a distributed RAM as the data hold memory. Each of the arithmetic operation circuits (L1 to L3) receives the input data (X), and outputs arithmetic operation result data (V1 to V3). A verification circuit (21) compares the arithmetic operation result data (V1 to V3) to verify whether errors occur.