External PLL FPGA Clock Alignment Without Domain Crossing
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Solution Overview
Problem
Field programmable gate arrays (FPGAs) face a technical challenge in synchronizing receiver and transmitter clock signals, which introduces unwanted latency and delays in processing, particularly in high-frequency applications like high-frequency trading where microsecond accuracy is crucial.
Innovation Solution
A field programmable gate array system with an external phase controller that aligns the receiver and transmitter clock signals without using clock domain crossing circuits, utilizing a deserializer and serializer to convert serial data streams into parallel streams and back, while an external phase control circuit adjusts the transmitter side clock to match the receiver side clock, eliminating the need for clock domain crossing and its associated latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock domain crossing circuits are used to synchronize receiver and transmitter clock signals, then phase synchronization is achieved, but processing latency increases
Solution Approach 1:
The patent extracts the clock domain crossing synchronization function from the FPGA fabric and implements it externally using a separate phase-locked loop circuit. This removes the latency-introducing circuitry from the critical data processing path while maintaining the necessary clock synchronization between receiver and transmitter domains.
Solution Approach 2:
The system segments the clock synchronization function into a separate external module rather than integrating it within the FPGA. The receiver clock domain and transmitter clock domain are handled by distinct circuits, with the external PLL providing the synchronization bridge without interfering with the internal data processing timeline.
2Reliability
If clock domain crossing circuits are included in the FPGA, then phase matching between receiver and transmitter clocks is achieved, but processing speed decreases
Solution Approach 1:
The clock domain crossing circuitry is extracted from the FPGA fabric and implemented externally. This allows the FPGA to operate at full speed for data processing while the external circuit handles the clock synchronization, eliminating the speed penalty that would result from including synchronization circuits within the FPGA's critical path.
3Reliability
If traditional phase synchronization methods are used, then clock signals are aligned, but unwanted latency is introduced
Solution Approach 1:
An external phase-locked loop circuit serves as an intermediary between the receiver and transmitter clock domains. This mediator provides the necessary phase alignment and frequency matching while introducing minimal latency, as it operates outside the critical data processing path of the FPGA.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables sub-microsecond processing throughput with minimal latency, supporting data rates from 10 Gbps to 120 Gbps without the delays introduced by traditional clock domain crossing methods, thus enhancing processing efficiency in high-frequency applications.
Implementation Method 1
a phase detector operationally connected to the first clock output pin and the second clock output pin of the second interface of the field programmable gate array, and wherein the phase detector is configured to compare the third phase of the receiver side clock signal to the fifth phase of the transmitter side clock signal and to generate a phase difference indicator signal based on a difference between the third phase of the receiver side clock signal and the fifth phase of the transmitter side clock signal
Implementation Method 2
an adjustable oscillator operationally connected to the phase controller and configured to receive the adjustment information as well as operationally connected to the second reference clock pin of the first interface of the field programmable gate array, wherein the adjustable oscillator is configured to generate the second clock signal including the second frequency and the second phase based on the adjustment information
Data Source
AI summary
The present invention relates to a field programmable gate array system that provides phase control with minimal latency.