FPGA Clock Circuit Using FLL Feedback for Low-Power Precision
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Solution Overview
Problem
Existing low-power FPGAs in measurement technology require a precise clock with minimal frequency deviation, but commercially available low-power oscillators cannot provide this accuracy, and integrated PLL circuits consume excessive power, making them unattractive for systems needing both low power and high precision.
Innovation Solution
A circuit comprising an FPGA with an FLL circuit, a programmable oscillator, and a series of selectively bridgeable resistors to control the oscillator's frequency, allowing for precise clock generation with reduced power consumption by adjusting resistance values to achieve a target frequency ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a PLL circuit is used to generate a precise clock signal, then frequency accuracy is improved, but power consumption increases significantly
Solution Approach 1:
Instead of using a PLL circuit that consumes high power (1 mA) to achieve frequency accuracy, the patent inverts the approach by using a low-power oscillator (80 μA) with an FLL circuit that monitors and adjusts the frequency through feedback, achieving the same precision goal with dramatically reduced power consumption.
Solution Approach 2:
The patent changes the control parameter from phase detection (PLL) to frequency counting (FLL), and adjusts the oscillator frequency dynamically by changing resistance values in the RC circuit, thereby achieving precise frequency control without the high power consumption of traditional PLL circuits.
2Use of energy by moving object
If a low-power oscillator is used to reduce power consumption, then energy efficiency is improved, but frequency accuracy deteriorates
Solution Approach 1:
The patent introduces an FLL circuit that continuously monitors the oscillator frequency by counting clock cycles against a reference clock and provides feedback control. This feedback mechanism allows the low-power oscillator to maintain frequency accuracy within ±0.1% or ±0.2% despite its inherently lower precision, by dynamically adjusting the frequency through resistance changes.
Solution Approach 2:
The patent replaces the traditional electronic feedback mechanism of PLL circuits with a digital counting and comparison system in the FLL circuit, which uses simple digital logic to monitor frequency and control resistance values, thereby achieving accurate frequency control with minimal power consumption.
3Adaptability or versatility
If the oscillator frequency is adjusted dynamically, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent segments the frequency control mechanism into discrete resistance values achieved through selectively bridgeable resistors. This segmentation allows the FLL circuit to control oscillator frequency in discrete steps by switching between different resistance combinations, achieving adaptability without requiring complex continuous control circuitry.
Solution Approach 2:
The patent implements dynamic frequency adjustment by making the resistance values controllable through the FLL circuit. The resistors can be selectively bridged or disconnected based on feedback from the frequency monitoring, allowing the oscillator frequency to adapt dynamically to maintain accuracy while keeping the control mechanism relatively simple.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a precise clock with minimal power consumption, reducing energy use by over 30 times compared to traditional PLL circuits while maintaining frequency accuracy within 1% variation, suitable for applications requiring low power and high precision.
Implementation Method 1
the FLL circuit is designed to capture a first number of clock signals of the programmable oscillator during a second number of periods of the reference clock
Implementation Method 2
the frequency of the programmable oscillator is controlled via at least one resistance value upon which the feedback signal applies
Implementation Method 3
the resistance value being adjustable via a series of individual resistors which are at least partially selectively bridgeable with respect to circuit ground to reduce the resistance
Data Source
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AI summary
A circuit 1 comprises: an FPGA 2, which has an FLL circuit 5; a reference clock generator 4 of a first frequency or a reference clock input for receiving a reference clock of the first frequency; a programmable oscillator 3, which outputs a clock signal for the FPGA 2, wherein the FLL circuit 5 is designed to detect a first number of clock signals of the programmable oscillator 4 during a second number of periods of the reference clock, wherein the first number is greater than the second number, and to output a feedback signal in order to control the ratio between the first number and the second number by virtue of the feedback signal acting on the frequency of the programmable oscillator.