FPGA Clock Signal Generation for Cycle-Accurate Hardware Acceleration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Simulating complex integrated circuits with Field Programmable Gate Arrays (FPGAs) faces challenges in cycle accuracy and reproducibility, particularly in mapping memory types and ensuring identical simulation results across different optimization levels, which hinders efficient debugging and speeds up the simulation process.
Innovation Solution
The method involves generating clock signals for FPGAs to match device-under-test (DUT) clock signals at multiple frequencies and ratios, using free-running and stoppable clocks, and synchronizing events to maintain cycle accuracy and reproducibility, with a single clock source generating all device clock signals and controlling memory operations to ensure consistent simulation states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware acceleration is used to speed up simulation, then simulation speed is improved, but cycle reproducibility becomes difficult to maintain
Solution Approach 1:
The patent applies preliminary action by pre-computing and storing the exact sequence of clock signals and memory operations that reproduce the software simulator's behavior. The hardware accelerator is configured with predetermined control logic that automatically replaying the exact same sequence of operations, ensuring cycle-reproducible results while maintaining high simulation speed through hardware parallelism.
2Measurement precision
If multiple memory types are mapped to FPGA memory, then cycle accuracy is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the complex memory mapping into separate, manageable components. Different FPGA memory blocks are dedicated to specific memory types (register arrays, SRAMs, DRAMs), with each segment handled by specialized control logic. This modular approach maintains cycle accuracy by preserving the distinct timing characteristics of each memory type while reducing overall design complexity through standardization.
Solution Approach 2:
The patent introduces an intermediary memory controller layer that mediates between the hardware accelerator and various memory types. This controller abstracts the complexity of mapping different memory types to FPGA resources, providing a unified interface that simplifies the connection between the accelerator core and memory subsystems while maintaining precise timing control for cycle-accurate simulation.
3Loss of time
If optimized simulation is used for speed, then simulation time is reduced, but debugging capability deteriorates
Solution Approach 1:
The patent applies dynamics by making the simulation system reconfigurable between different operational modes. The same hardware accelerator can dynamically switch between optimized mode (for speed) and debug mode (for detailed tracing and single-stepping). This is achieved through configurable control logic that adjusts the level of instrumentation and optimization, allowing users to switch between performance and debugging requirements without hardware changes.
Data Source
AI summary
A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.