FPGA Data Path Clock Selection Using Latency Tables
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Solution Overview
Problem
Existing methods for programming FPGAs face challenges in achieving minimal throughput time due to the non-linear relationship between clock frequency, latency, and bit width, leading to suboptimal clock rates and increased development times.
Innovation Solution
A method involving a library of elementary operations with pre-created latency tables for various clock rates and bit widths, allowing for the calculation of total latency for data paths and selection of optimal clock rates to minimize throughput time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock frequency of the FPGA is increased to achieve faster control loops, then the processing speed is improved, but the number of clock cycles required for operations must be increased, which offsets the gain
Solution Approach 1:
The patent applies parameter changes by systematically varying clock frequency, latency, and bit width parameters to find optimal configurations. Latency tables store pre-calculated optimal parameters for different operation types and bit widths, allowing the system to select parameters that minimize throughput time rather than simply increasing clock frequency.
Solution Approach 2:
The patent uses preliminary action by pre-calculating and storing latency tables for different elementary operations, clock rates, and bit widths before actual FPGA programming. These pre-computed tables contain optimal latency values that guide the selection of clock rates and operation configurations, eliminating the need for trial-and-error optimization during implementation.
2Adaptability or versatility
If manual hardware description is used to define FPGA circuit structure, then customization and parallelism are achieved, but development and verification times increase significantly with complexity
Solution Approach 1:
The patent uses copying by creating reusable latency tables that contain pre-defined latency information for standard elementary operations. Instead of manually characterizing each operation, the system copies and applies pre-measured latency data from tables, significantly reducing the time required to develop and verify custom FPGA configurations while maintaining adaptability.
Solution Approach 2:
The patent applies parameter changes by allowing developers to specify high-level parameters (operation type, bit width, clock rate) without manually defining circuit structures. The system automatically selects optimal latency parameters from pre-computed tables, reducing manual effort while maintaining customization capability through parameter specification.
3Extent of automation
If conventional FPGA programming tools are used, then automation of HDL code generation is achieved, but optimal clock rates cannot be determined due to non-linear relationships between clock frequency, latency, and bit width
Solution Approach 1:
The patent introduces an intermediary element - latency tables - that bridge the gap between automated code generation and optimal clock rate determination. These tables contain pre-calculated latency data that mediate between the automated programming tools and the FPGA implementation, providing the missing optimization information that conventional tools cannot generate due to non-linear relationships.
Solution Approach 2:
The patent applies preliminary action by pre-computing latency tables that contain optimal clock rate information for different operation types and bit widths. This preliminary characterization work is performed once and reused across multiple programming tasks, enabling automated tools to select optimal clock rates without having to perform complex non-linear optimization calculations during each programming session.
Data Source
AI summary
A method for programming an FPGA, wherein a library, which includes elementary operations and a particular latency table for each of the elementary operations of the library is provided. Each latency table indicates the latency of the particular operation for a plurality of clock rates of the FPGA and for a plurality of input bit widths of the particular operation during the execution on the FPGA, depending on the input bit width of the particular operation and the clock rate of the FPGA. A data path indicating a consecutive execution of at least two elementary operations of the library on the FPGA is defined. The latencies given for the particular input bit width of the particular elementary operations of the data path for a plurality of different clock rates in the latency tables are detected and added, then one of the clock rates is selected.