FPGA Clock Model for IC Emulation Glitch Mitigation
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Solution Overview
Problem
The challenge in IC design is that glitches in generated clocks due to circuit delay cause errors in sequential cells when directly applied to an FPGA, as the pre-wired semi-custom nature of FPGA prevents control of glitch generation through wiring length adjustment.
Innovation Solution
A method involving converting IC design into a directed graph, substituting sequential cells with clock models [CA] and [CB], and configuring phase shifts for primary clocks to eliminate glitches, ensuring correct data sampling without introducing combinatorial logic delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If IC design is directly applied on FPGA, then emulation can be performed, but glitch-caused error data sample output by sequential cell cannot be avoided
Solution Approach 1:
The patent introduces a clock model as an intermediary component between the generated clock and the sequential cell. This clock model includes a clock detector that detects the active edge of the user clock and generates a detected clock signal, which then triggers the sequential cell. This intermediary mechanism isolates the sequential cell from glitch-containing generated clocks while preserving the intended sampling behavior, thus resolving the contradiction between maintaining emulation capability and ensuring data sampling accuracy.
2Manufacturing precision
If strict wiring design is used in IC design, then glitch generation can be controlled, but FPGA pre-wired semi-custom nature prevents this control
Solution Approach 1:
The patent changes the parameter of clock signal generation from physical wiring delay control (which works in IC design) to logical timing control through a clock model. The clock model uses a clock detector to monitor the user clock and generate a detected clock signal with proper timing characteristics, independent of physical wiring delays. This parameter change enables glitch control in the logical domain rather than relying on physical wiring precision, making the design adaptable to FPGA's pre-wired semi-custom nature while maintaining glitch control capability.
3Ease of operation
If generated clocks with glitches are connected to sequential cell clock input, then clock structure functionality is maintained, but sequential cell is mistakenly triggered causing error output
Solution Approach 1:
The patent introduces a clock model as an intermediary component between the user clock and the sequential cell. The clock model contains a clock detector that monitors the user clock signal and generates a detected clock signal only when the active edge is properly detected. This intermediary mechanism filters out glitch-containing clock signals while preserving the intended clocking functionality, allowing the sequential cell to be triggered only by valid clock edges and preventing erroneous outputs.
Data Source
AI summary
The invention relates to the technical field of electronic design automation (EDA), especially relates to a method and a system for emulating an IC design with an FPGA, and a storage medium. It is characterized by substituting clock models for the sequential cells; adding a user enable to an external port of a clock model compared to the port of a sequential cell in the IC design, through a user clock to which a user enable of a clock model is connected and a primary clock′ to which a clock input of a clock model is connected, a clock model[CA] reproducing the function of the sequential cell in the IC design by controlling outputting time of a data sample, and the clock model[CB] reproducing the function of the sequential cell in the IC design by controlling data sampling time; and configuring phase shifts for primary clocks' by which the clock model[CA] and the clock model[CB] are driven, so as to solve the technical problem of sampling error due to presence of the user clock while ensuring the functions of the original sequential cells.