FPGA Clock Data Recovery Circuit for Semiconductor Testing
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Solution Overview
Problem
Current semiconductor device testing methods face challenges in accurately obtaining clock data, which is essential for the operation of semiconductor devices, due to the complexity of modern electronic equipment and the need for efficient signal processing.
Innovation Solution
A test device comprising a comparison circuit, a field programmable gate array (FPGA), a sampling circuit, an edge extraction circuit, an edge combining circuit, and a filter circuit, which generates comparison signals, sample data signals, edge data signals, combined edge data, and ultimately recovers clock data by filtering the combined edge data, utilizing symbol sequences embedded in input signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a custom ASIC is used for clock data recovery, then the manufacturing precision and reliability are improved, but the development time and cost increase
Solution Approach 1:
The patent uses an FPGA to implement a reconfigurable clock data recovery circuit that copies the functionality of custom ASIC designs. The FPGA allows rapid prototyping and testing of clock recovery algorithms without the lengthy ASIC development cycle, while maintaining comparable reliability through programmable precision control.
Solution Approach 2:
The patent employs dynamic parameter adjustment in the clock data recovery circuit implemented on FPGA. The circuit can adaptively adjust sampling points, clock frequencies, and recovery parameters in real-time, providing the reliability of custom designs with the flexibility and faster development of reconfigurable logic.
2Adaptability or versatility
If conventional circuitry is used for clock recovery, then the area and power consumption are reduced, but the adaptability and functionality are limited
Solution Approach 1:
The patent implements a universal clock data recovery circuit on FPGA that can handle multiple input signal types, data rates, and protocols. The reconfigurable architecture allows a single circuit to perform multiple clock recovery functions, providing high adaptability while using less area than implementing multiple dedicated circuits.
Solution Approach 2:
The patent utilizes programmable parameter adjustment in the FPGA-based clock recovery circuit. Key parameters such as sampling frequency, clock frequency, and recovery algorithm coefficients can be dynamically changed through configuration, enabling the same hardware to adapt to different applications without increasing physical area.
3Measurement precision
If complex signal processing is performed to accurately recover clock data, then the measurement precision is improved, but the use of energy and device complexity increase
Solution Approach 1:
The patent performs preliminary signal conditioning and preprocessing in the comparison circuit before the main clock recovery operation. By pre-processing the input signals to enhance their quality and extract relevant features early in the signal chain, the subsequent clock recovery stage requires less complex processing and consumes less energy while maintaining high measurement precision.
Data Source
AI summary
A test device includes a comparison circuit configured to receive a plurality of input signals and generate a plurality of comparison signals based on the plurality of input signals; and a field programmable gate array (FPGA) configured to recover clock data, based on the plurality of comparison signals, wherein the FPGA includes a sampling circuit configured to generate a plurality of sample data signals by sampling the plurality of comparison signals; an edge extraction circuit configured to generate a plurality of edge data signals, based on logic values of bits in the plurality of sample data signals; an edge combining circuit configured to generate combined edge data by performing a logic operation on the plurality of edge data signals; and a filter circuit configured to recover the clock data by filtering the combined edge data.