FPGA Clock Skipping Control for Voltage Droop Mitigation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Voltage droop on power rails of integrated circuit devices, such as programmable logic devices, is a challenge due to changes in current draw causing power supply noise, which can be mitigated by additional silicon, packaging, and decoupling capacitors but at the cost of space and design complexity.
Innovation Solution
Implementing a clock skipping scheme in the FPGA design via an EDA tool to adjust clock skipping cycles based on current ramp-up speed and clock frequency, maintaining base clock frequency, and reducing power consumption while alleviating the need for additional hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional silicon, packaging, and decoupling capacitors are added to mitigate voltage droop, then voltage stability is improved, but device complexity and space consumption increase
Solution Approach 1:
The patent replaces the mechanical/hardware approach (adding decoupling capacitors and power supply infrastructure) with a software/control approach (clock skipping mechanism). The system dynamically adjusts clock operation to control current draw and mitigate voltage droop without additional hardware, thereby resolving the contradiction between voltage stability and device complexity.
Solution Approach 2:
The patent changes the operational parameters of the clock system by implementing dynamic clock skipping. The clock skipping factor is adjusted based on detected voltage droop conditions, allowing the system to modulate current consumption and maintain voltage stability. This parameter-based control avoids the need for additional hardware components.
2Object-affected harmful factors
If additional decoupling capacitors and power supply infrastructure are added, then power supply noise is reduced, but space consumption increases
Solution Approach 1:
The patent substitutes physical power supply infrastructure (decoupling capacitors, power rails) with a control mechanism that manages electrical characteristics through software. By dynamically skipping clock cycles based on power supply conditions, the system reduces power supply noise without requiring additional physical components, thereby resolving the space consumption issue.
3Loss of energy
If clock skipping is implemented to reduce current draw and voltage droop, then power consumption is reduced, but timing closure becomes more complex
Solution Approach 1:
The patent implements a feedback mechanism where the system continuously monitors voltage droop conditions and adjusts clock skipping accordingly. The clock skipping factor is dynamically modified based on real-time power supply status, allowing the system to reduce power consumption while maintaining timing integrity through adaptive control rather than fixed complex timing schemes.
Data Source
AI summary
To mitigate voltage droop while reducing the power and space consumed on the board and reducing switching activity, a clock skipping scheme may be implemented for an FPGA. The clock skipping scheme may be implemented in the FPGA design via an Electronic Design Automation (EDA) tool. The EDA tool may define clock skipping cycles based on customer needs for current ramp up speed (e.g., for an inrush current or an operating current) and clock frequency. The EDA tool may adjust clock skipping based on a power target and/or usage conditions of a user software design. In addition to mitigating voltage droop and reducing space consumed on the board and power consumed by the FPGA, the clock skipping scheme may maintain a base clock frequency, enable timing closure at the base clock frequency, and alleviate the need to reclose timing during clock skipping operations.