Configurable Clock Timing Analysis for FPGA Design Closure
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Solution Overview
Problem
In system design for target devices like FPGAs and ASICs, achieving timing closure is challenging, requiring multiple iterations of design modifications and analysis, which is time-consuming and inefficient.
Innovation Solution
The method involves pre-timing clocks associated with interface logic and analyzing/adjusting compiler-generated logic clocks to ensure the system operates within specified frequency constraints, using a configurable clock that is programmed to drive the system at its maximum feasible frequency, identified through timing analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional iterative design modification is used to achieve timing closure, then timing constraints can be met, but the design process becomes time-consuming and inefficient
Solution Approach 1:
The patent applies preliminary action by pre-timing clocks associated with interface logic before the main compilation process. This allows timing constraints to be established in advance, eliminating the need for multiple iterative design modifications later in the process, thereby reducing overall design time while ensuring timing closure.
Solution Approach 2:
The patent segments the timing analysis process into distinct phases: pre-timing interface logic clocks separately from compiler-generated logic clocks. This segmentation allows each component to be optimized independently, with interface logic pre-timed and compiler logic adjusted afterward, reducing the need for complete redesign iterations.
2Device complexity
If all clocks are treated uniformly in timing analysis, then the analysis process is simple, but it cannot optimize for different clock types and their specific constraints
Solution Approach 1:
The patent applies local quality by treating different clock types differently in the timing analysis. Interface logic clocks receive pre-timing treatment with hard constraints, while compiler-generated logic clocks receive iterative adjustment. This localized differentiation optimizes each clock type according to its specific requirements without overly complicating the overall analysis process.
Data Source
AI summary
A method for designing a system on a target device includes describing the system in a high-level synthesis language where the system includes a configurable clock to drive the system at a specified clock frequency. A hardware description language (HDL) of the system is generated from the high-level synthesis language. An initial compilation of the HDL of the system is performed in response to the specified clock frequency. Timing analysis is performed on the system after the initial compilation of the HDL to determine a maximum frequency which the system can be driven. The configurable clock is programmed to drive the system at the maximum frequency.