FPGA Configuration Clocking with Delayed Capture Edge
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Solution Overview
Problem
The configuration time for programmable logic devices like FPGAs is limited by the delay in the I/O circuitry and the speed of data access from external storage devices, leading to inefficiencies that discourage their use in favor of application-specific integrated circuits.
Innovation Solution
A method and system that delay the capture edge of a clock signal to synchronize data receipt in a data latch, using consecutive clock edges and embedding delay cells to compensate for delays between the launch and capture of data, allowing the same clock edge to clock both the storage device and the data latch, thereby reducing the configuration time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is read synchronously from external storage device, then data access is reliable and synchronized with clock signal, but configuration time is increased due to I/O circuitry delay and storage device access speed
Solution Approach 1:
The patent applies preliminary action by launching data from the storage device before the capture edge arrives. The launch edge triggers data output from the storage device in advance, allowing the data to be prepared and transferred through the I/O circuitry before the capture edge requires it at the data latch. This overlapping of operations reduces the total configuration time while maintaining reliable synchronization.
Solution Approach 2:
The patent introduces dynamic timing adjustment by using separate launch and capture edges with different timing relationships. The clock signal is configured with specific timing parameters where the launch edge occurs at one phase and the capture edge at another, allowing the system to dynamically optimize the data transfer window. This dynamic timing approach enables faster configuration while preserving data integrity.
2Ease of operation
If I/O circuitry is included for data communication, then data transfer between storage device and integrated circuit is enabled, but delay is introduced that slows down configuration speed
Solution Approach 1:
The I/O circuitry is utilized more efficiently by launching data through it in advance of when it is needed. The preliminary data launch through the I/O circuitry allows the communication infrastructure to be fully exploited without becoming a speed bottleneck, as the data is prepared and transmitted through the I/O paths before the capture operation begins.
Solution Approach 2:
The patent maintains continuous useful action by overlapping the data launch and capture operations. The I/O circuitry remains continuously utilized during the configuration process, with data being launched and transferred through the communication paths while the clock signal progresses through its cycle, eliminating idle time in the data communication chain.
3Quantity of substance
If configuration data is stored in external storage device, then storage capacity is sufficient for configuration information, but access speed from storage device limits overall configuration performance
Solution Approach 1:
The storage device is accessed in advance by triggering data launch with the launch edge before the capture edge occurs. This preliminary access allows the storage device to begin retrieving configuration data earlier in the clock cycle, effectively hiding the access delay within the clock period and improving overall configuration speed while maintaining full storage capacity utilization.
Data Source
AI summary
Provided is a method and system to transmit data to a configurable integrated circuit that features delaying a capture edge of a clock signal at a data latch to synchronize the receipt of data at the data latch that was transmitted in response to a storage device receiving a launch edge of the clock signal. The method includes transmitting the clock signal having the launch edge and the capture edge to the storage device. The data is launched from the storage device to the integrated circuit in response to the storage device sensing the launch edge. Receipt of the capture edge at the data latch is delayed for a predetermined time to compensate for a delay between transmitting the launch edge and launching the data to ensure the data is latched by the data latch. Also disclosed is a system that carries out the function of the method.