FPGA Clocking Circuit Using FLL Feedback for Low-Power Precision
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Solution Overview
Problem
Existing FPGA clocking systems face challenges in achieving precise clocking with low power consumption, as commercially available oscillators and integrated PLL-circuits consume excessive power, making them unsuitable for applications requiring precise clocking in measurement technology.
Innovation Solution
A circuit incorporating an FLL-circuit, a digitally controlled oscillator, and a feedback mechanism to control the frequency ratio between the oscillator and reference clock, utilizing a resistor network for adjustable resistance values to minimize power consumption while maintaining precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a PLL-circuit is used to generate precise clock signal, then clock precision is improved, but power consumption increases significantly
Solution Approach 1:
The patent changes the fundamental operating parameters of the frequency control system by replacing the PLL architecture with an FLL (Frequency Locked Loop) approach. The FLL circuit counts a first number of clock signals from the digitally controlled oscillator during a second number of periods of the reference clock, where the first number is larger than the second number, creating a frequency division relationship. This parameter change allows the system to achieve precise frequency control with much lower power consumption while maintaining the required clock precision for measurement technology applications.
Solution Approach 2:
The patent substitutes the traditional PLL mechanical/electrical system with a digitally controlled oscillator and FLL counting system. Instead of using phase detection and continuous feedback adjustment typical of PLL circuits, the invention uses digital counting of clock cycles and feedback based on the counted ratio, replacing the continuous analog feedback mechanism with a discrete digital counting approach that consumes significantly less power.
2Measurement precision
If a digitally controlled oscillator with high frequency multiplication is used, then clock precision is improved, but frequency stability becomes difficult to maintain
Solution Approach 1:
The patent implements a feedback mechanism where the FLL circuit provides feedback signals based on the counted ratio of clock signals to reference clock periods. The feedback signal adjusts the digitally controlled oscillator to maintain the desired frequency ratio (N:M where N>M). This closed-loop feedback ensures frequency stability even when achieving high frequency multiplication ratios (10:1, 100:1, or 500:1), as the system continuously corrects deviations from the target frequency relationship.
Solution Approach 2:
The patent introduces dynamic adjustment capabilities through the feedback-controlled digitally controlled oscillator. The system can dynamically adjust the oscillator frequency in response to feedback from the FLL counting mechanism, allowing the system to adapt to variations while maintaining stable operation. The dynamic nature of the control allows the system to maintain stability across different operating conditions and frequency ratios.
Data Source
AI summary
The circuit for the clocking of an FPGA comprises an FLL-circuit; a reference clock of a first frequency, or a reference clock input for the reception of a signal of a reference clock of a first frequency; and a digitally controlled oscillator, which outputs a clocking signal for the FPGA, wherein the FLL-circuit is designed in order to register a first number of clocking signals from the digitally controlled oscillator during a second number of periods of the reference clock, the first number is larger than the second number, and, in order to give out a feedback signal to control the ratio between the first number and the second number, as the feedback signal acts on the frequency of the digitally controlled oscillator.