FPGA Clos Network Input Interconnect Routing

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Solution Overview

Problem

Existing FPGA interconnect architectures, particularly those based on Clos networks, face performance degradation and high implementation costs due to the requirement for non-blocking networks, which are impractical for programmable logic devices and fail to exploit locality for area savings.

Innovation Solution

A three-stage Clos network architecture with specific parameter relationships (m < n1) is used for internal cluster routing in FPGAs, allowing for high routability without the need for non-blocking capabilities, and incorporating flexibility in other routing fabric portions to manage blocking cases, along with the use of fast connections to enhance network efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a non-blocking Clos network architecture is used to ensure high routability, then signal routing flexibility is improved, but area consumption and implementation cost increase significantly

Engineering Contradiction:

Improverouting flexibilityVSAvoidinterconnect area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent applies partial non-blocking action by making only the first stage of the Clos network non-blocking (n1 ≥ m), while allowing blocking in subsequent stages. This partial approach provides sufficient routing flexibility for most signals while reducing the overall area requirement compared to a fully non-blocking network, directly resolving the contradiction between routing flexibility and area consumption.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The Clos network is segmented into multiple stages with different blocking characteristics. The first stage uses n1 ≥ m to provide non-blocking access to cluster inputs, while later stages can operate with blocking. This segmentation allows the system to achieve adequate routing flexibility without the full area penalty of a completely non-blocking architecture.

Inventive Principle:

Principle #1Segmentation

2Productivity

If the number of crossbar outputs (m) is increased to reduce blocking, then routing performance is improved, but the number of required crossbars and area consumption increase

Engineering Contradiction:

Improverouting performanceVSAvoidnetwork structure complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent changes the parameter relationship in the first stage to n1 ≥ m, which is opposite to the traditional Clos network constraint (m ≥ n1). This parameter change allows the first stage crossbars to have more inputs than outputs, reducing the need for numerous crossbars while maintaining routing performance through the non-blocking property of the first stage.

Inventive Principle:

Principle #35Parameter changes

3Device complexity

If a traditional Clos network with m ≥ n1 is used, then the network structure is simplified, but routing flexibility and performance degrade

Engineering Contradiction:

Improvenetwork structure simplicityVSAvoidrouting flexibility

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent inverts the traditional Clos network parameter constraint by using n1 ≥ m instead of m ≥ n1 in the first stage. This inversion allows the network to achieve better routing flexibility and performance while maintaining reasonable structural simplicity, as the first stage becomes the bottleneck rather than the later stages.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS7924052B1Field programmable gate array architecture having Clos network-based input interconnect

Publication Date: 2011.04.12 MICROSEMI SOC CORP

AI summary

A cluster internal routing network for use in a programmable logic device with a cluster-based architecture employs a Clos network-based routing architecture. The routing architecture is a multi-stage blocking architecture, where the number of inputs to the first stage exceeds the number of outputs from the first stage.