FPGA Cluster Accelerates Homomorphic Encryption Relinearization
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Solution Overview
Problem
Current homomorphic encryption techniques are slow due to high computation overhead, and existing FPGA-based accelerators like HEAX face resource limitations, leading to inefficient processing and limited scalability for large parameter sets.
Innovation Solution
A cluster of FPGAs is used to accelerate homomorphic encryption by breaking down processes into parallel operations across multiple FPGA devices, each specializing in inverse number-theoretic transform, number-theoretic transform, multiplication, and residue number system functions, with optimized communication protocols to enhance throughput and resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single FPGA is used for homomorphic encryption acceleration, then device complexity is reduced, but processing speed and scalability deteriorate
Solution Approach 1:
The patent divides the homomorphic encryption processing system into multiple separate FPGA devices, each dedicated to specific computational tasks (NTT, INTT, multiplication, etc.). This segmentation allows parallel processing across multiple devices, significantly improving processing speed while keeping each individual FPGA relatively simple in configuration.
2Productivity
If more FPGA resources are allocated to handle large parameter sets, then processing capability improves, but resource limitations and scalability issues worsen
Solution Approach 1:
The patent transitions from a single-dimension approach (one FPGA handling all tasks) to a multi-dimensional distributed architecture where multiple FPGAs work in parallel. This dimensional change allows the system to handle large parameter sets (N>=8192, q>=200) by distributing the computational burden across multiple devices, effectively overcoming the resource limitations of a single FPGA.
3Productivity
If parallel processing is implemented across multiple FPGAs, then throughput improves, but communication overhead and system complexity increase
Solution Approach 1:
The patent introduces a host computer as an intermediary that coordinates the parallel processing across multiple FPGAs. The host manages data distribution, coordinates computational tasks, and aggregates results, thereby simplifying the communication protocol requirements between FPGAs while maintaining high throughput through efficient parallel execution.
Data Source
AI summary
A field-programmable gate array (FPGA) cluster, comprising a plurality of FPGA devices, can be used to accelerate homomorphic encryption functionality. In particular, the FPGA cluster can accelerate the relinearization process used in homomorphic encryption by using multiple FPGA devices to perform portions of the relinearization process in parallel. Further, the use of the FPGA cluster provides sufficient memory resources to allow data used by the relinearization process, namely the keyswitch keys, to be stored on-chip.