FPGA Interface Circuitry for CML-to-Voltage Mode M-PHY Testing
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Solution Overview
Problem
Current field programmable gate arrays (FPGAs) with current mode logic (CML) transceivers are incompatible with voltage mode logic-based devices, such as those using the MIPI M-PHY specification, hindering efficient IC development and testing due to incompatibility in electrical signaling modes.
Innovation Solution
Implementing interface logic using off-the-shelf components and RF modules to enable CML transceivers in FPGAs to emulate voltage mode electrical attributes, allowing compatibility with voltage mode transceivers and enabling communication with devices adhering to the MIPI M-PHY specification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If CML transceivers are used in FPGAs, then high-speed communication capability is achieved, but compatibility with voltage mode logic devices is lost
Solution Approach 1:
The patent introduces an interface circuit as an intermediary component between the CML transceiver in the FPGA and the voltage mode logic device. This interface circuit performs signal level translation and impedance matching, converting CML signals to voltage mode signals and vice versa, thereby enabling compatibility between the two different electrical signaling modes while preserving the high-speed communication capability of the CML transceiver
Solution Approach 2:
The interface circuit dynamically adjusts electrical parameters such as signal voltage levels, impedance, and common-mode voltage to match the requirements of the connected device. By changing these parameters based on the detected signaling mode, the system achieves adaptability between CML and voltage mode logic devices without sacrificing communication speed
2Adaptability or versatility
If ASIC design and fabrication are performed to achieve electrical compatibility, then compatibility with voltage mode devices is achieved, but development cost and time increase significantly
Solution Approach 1:
The patent makes the FPGA system universal by enabling it to interface with multiple types of devices (both CML and voltage mode logic devices) through a single reconfigurable interface circuit. This eliminates the need for separate ASIC designs for different device types, allowing one FPGA platform to serve multiple purposes and reducing overall development time and cost
Solution Approach 2:
Instead of creating custom ASIC hardware for each compatibility requirement, the patent uses software-based protocol emulation and configuration in the FPGA to replicate the electrical characteristics of different signaling modes. This software copying approach is much faster and more cost-effective than physical ASIC fabrication while achieving the same compatibility goals
3Adaptability or versatility
If ASIC design and fabrication are performed to achieve electrical compatibility, then compatibility with voltage mode devices is achieved, but development cost increases
Solution Approach 1:
The patent replaces expensive, fixed-function ASIC designs with reconfigurable FPGA-based interface circuits that can be programmed and reprogrammed as needed. While FPGAs have higher unit cost than ASICs, the elimination of multiple ASIC design iterations, mask sets, and fabrication runs results in significant overall cost reduction, especially for low-to-mid volume production and rapid prototyping
Data Source
AI summary
In one embodiment, a test apparatus includes a field programmable gate array (FPGA) including a first transmitter to communicate first signals according to current mode logic (CML) signaling and a first receiver to receive second signals according to the CML signaling, and an interface circuit to couple the FPGA to a device that is to communicate according to voltage mode signaling. The interface circuit may adapt the first signals communicated by the first transmitter according to the CML signaling to voltage mode signaling signals for receipt by the device. Other embodiments are described and claimed.