Automated FPGA Code Optimization via Dataflow Graphs
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Solution Overview
Problem
Current high-level synthesis (HLS) tools require significant expertise and manual effort to optimize software code for FPGA hardware accelerators, limiting their accessibility and efficiency, especially in generating optimized hardware implementations that leverage concurrent execution and energy savings.
Innovation Solution
A method that uses a dataflow graph representation of computations, obtained through instrumentation of critical functions, to automatically restructure C code and generate HLS-friendly code with directives, enabling efficient hardware acceleration without requiring extensive HLS expertise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If manual code restructuring and manual insertion of HLS directives are used to optimize FPGA hardware implementations, then hardware optimization performance is improved, but development time and expertise requirements increase
Solution Approach 1:
The system performs self-service by automatically analyzing source code, generating dataflow graphs, applying optimizations, and producing optimized HLS code without requiring manual intervention from experts. The automated pipeline includes source code parsing, dataflow graph generation, optimization application, and code generation, eliminating the need for manual code restructuring and directive insertion while maintaining high hardware optimization performance
Solution Approach 2:
The patent replaces the mechanical process of manual code restructuring with an automated computational system. Instead of developers manually analyzing and rewriting code, the system uses automated algorithms to parse source code, construct dataflow graphs, apply transformations, and generate optimized HLS code, substituting human expertise with automated mechanical processing
2Ease of operation
If high-level synthesis tools are used to program FPGAs with C code, then ease of programming is improved, but the ability to generate optimized hardware implementations deteriorates without manual restructuring
Solution Approach 1:
The patent introduces an intermediary system between the high-level C code and the FPGA hardware. This intermediary automatically generates dataflow graphs from C source code, applies optimizations to these graphs, and produces optimized HLS code. The intermediary layer bridges the gap between ease of C programming and hardware optimization performance, eliminating the need for manual code restructuring while maintaining both accessibility and optimization quality
3Productivity
If code restructuring optimizations are applied to C code for FPGA, then hardware execution performance is improved, but the complexity of the coding process increases
Solution Approach 1:
The patent replaces complex manual coding processes with automated mechanical systems. The system automatically performs code restructuring, dataflow graph generation, optimization application, and HLS code generation. This substitution eliminates the complexity burden from developers while maintaining high hardware execution performance through systematic automated transformations
Data Source
AI summary
A method for the generation of a hardware accelerator (20) is described. The method comprises inputting (110) a program (105) with a plurality of lines of code describing an algorithm to be implemented on the hardware accelerator (20) and generating (125) a dataflow graph in memory from the inputted program (105). The dataflow graph is optimized and an output program (140) created from the dataflow graph is output. The output program (140) is then provided to a high-level synthesis tool for generating the hardware accelerator (20).