FPGA Coefficient Generator for Real-Time Fading Channel Simulation

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Solution Overview

Problem

Conventional channel modeling for simulating communication systems in hardware is inefficient, particularly for multi-path fading channels, leading to significant simulation runtime and complexity in software-based approaches.

Innovation Solution

A coefficient generator is implemented in a programmable logic device, using a memory for storing constants and an Inverse Fourier Transform block to generate phase noise, filter it, and perform an Inverse Discrete Fourier Transform to produce noise-shaped responses for simulating communication channels in real-time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If software-based channel modeling is used, then flexibility and ease of implementation are improved, but simulation runtime and computational complexity increase significantly

Engineering Contradiction:
Improveease of implementationVSAvoidsimulation runtime
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent replaces software-based channel modeling with a hardware implementation using an FPGA. The coefficient generator circuit performs noise shaping and channel simulation through hardware components including phase noise sources, filters, and Inverse Fourier Transform blocks, eliminating the need for software execution and significantly reducing simulation runtime while maintaining flexibility through programmable logic configuration

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Loss of time

If hardware-based channel modeling is implemented, then simulation runtime is reduced, but device complexity and implementation difficulty increase

Engineering Contradiction:
Improvesimulation runtimeVSAvoidimplementation complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent divides the channel modeling function into separate modular components within the FPGA: phase noise sources, bandpass filters, constant memory storage, and Inverse Fourier Transform blocks. Each component handles a specific aspect of noise shaping, allowing the complex overall function to be implemented through simpler, independent hardware modules that can be configured and optimized separately

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses programmable logic to configure the behavior of the coefficient generator by changing parameters such as filter coefficients, noise characteristics, and transformation parameters. This allows the same hardware structure to model different channel conditions by reconfiguring logic parameters rather than requiring different hardware circuits for each simulation scenario

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If multi-path fading channel modeling is performed, then accuracy of system performance evaluation is improved, but computational complexity and runtime increase

Engineering Contradiction:
Improveaccuracy of system performance evaluationVSAvoidcomputational complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements multi-path fading modeling by periodically generating and processing noise samples through the hardware circuit. The phase noise sources generate periodic noise patterns that are filtered and transformed to create realistic fading channel characteristics, allowing accurate simulation of multiple propagation paths through repeated cyclic operations rather than complex one-time calculations

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS7599430B1Fading channel modeling
Publication Date: 2009.10.06 XILINX INC
  • US7599430B1 patent drawing
  • US7599430B1 patent drawing
  • US7599430B1 patent drawing

AI summary

Simulation of noise and, more particularly, a coefficient generator for channel modeling, is described. A spectrum memory is for storing sets of constants for respective harmonics. At least one phase noise source is configured for generating phase noise. An Inverse Fourier Transform block is coupled to the spectrum memory and to the at least one phase noise source. The Inverse Fourier Transform block is configured to provide a read address to the spectrum memory for accessing at least one constant of a set of constants of the sets of constants from the spectrum memory and coupled to receive the phase noise from the at least one phase noise source.