High-Level Language Compiler for FPGA Configuration
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Solution Overview
Problem
Current programmable logic devices require knowledge of hardware description languages like VHDL or Verilog for complex logic implementations, which can be inefficient and impractical for users not proficient in these languages, especially when implementing flow control elements.
Innovation Solution
The use of high-level programming languages such as OpenCL, where kernels are compiled into hardware circuits, and predicated instructions are optimized to reduce hardware size and latency, allowing for efficient configuration of programmable devices like FPGAs without the need for low-level language expertise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If hardware description languages (VHDL/Verilog) are used to configure programmable devices, then logic implementation capability is improved, but user accessibility and ease of operation deteriorate
Solution Approach 1:
The patent introduces a high-level language compiler as an intermediary tool that translates user-friendly high-level code into hardware description language. This mediator allows users to work with familiar programming languages while the compiler handles the complex HDL generation, thus improving accessibility without sacrificing implementation capability
Solution Approach 2:
The patent replaces manual HDL writing (mechanical process) with automated compiler-based translation. By substituting the manual mechanical process of writing HDL with an automated compilation process, users can leverage existing high-level language skills without needing to learn complex hardware description languages
2Adaptability or versatility
If flow control elements are implemented in programmable devices using traditional methods, then functionality is improved, but hardware size and latency increase
Solution Approach 1:
The patent extracts flow control functionality from traditional hardware implementation and represents it in high-level language constructs. By taking out the complex hardware flow control logic and expressing it in software-like high-level code, the compilation process can optimize the resulting hardware to be more compact and efficient
Solution Approach 2:
The patent changes the representation parameters of flow control from hardware-level signals and states to high-level language constructs. This parameter change allows the compiler to apply optimization techniques that reduce the resulting hardware size while maintaining the same functional behavior
3Adaptability or versatility
If traditional programming software is used to configure programmable devices, then logic layout capability is improved, but configuration time and complexity increase
Solution Approach 1:
The patent performs preliminary actions by using the compiler to automatically generate optimized hardware descriptions from high-level code before synthesis. This preliminary compilation and optimization step reduces the overall configuration time by preparing the hardware description in advance with optimizations already applied
Solution Approach 2:
The patent replaces manual logic layout and configuration processes with automated compiler-based generation. By substituting the mechanical process of manual HDL writing and configuration with automated compilation, the system maintains full logic layout capability while dramatically reducing configuration time
Data Source
AI summary
A method of programming or configuring an integrated circuit device using a high-level language includes parsing a logic flow to be embodied in the integrated circuit device to identify branching control flow, converting the branching control flow into predicated instructions, incorporating the predicated instructions into a high-level language representation of a configuration of resources of the integrated circuit device, and compiling the high-level language representation to configure said integrated circuit device. The high-level language representation can be executed to generate a configuration bitstream for the programmable integrated circuit device, or can be run on a processor on the programmable integrated circuit device to instantiate the configuration.