FPGA Configuration Bit Circuit Using MRAM or ReRAM Cells
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Solution Overview
Problem
Conventional configuration bits in field-programmable gate arrays (FPGAs) face issues with performance, security, and scalability, particularly due to the use of external non-volatile memory which is vulnerable to radiation and requires significant peripheral circuitry, and Flash memory is not scalable to small-scale technologies.
Innovation Solution
Implementing magnetoresistive random-access memory (MRAM) or resistive random-access memory (ReRAM) as configuration bits within the FPGA, allowing for multi-time or one-time programmable options that reduce the need for external storage and peripheral circuitry, enhancing security and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If external non-volatile memory is used to store configuration bits, then non-volatile storage is achieved, but security is compromised and peripheral circuitry complexity increases
Solution Approach 1:
The patent extracts the non-volatile storage function from external memory and implements it directly within the FPGA fabric using embedded non-volatile memory cells. This eliminates the external memory interface and associated security vulnerabilities while maintaining non-volatile configuration bit storage.
Solution Approach 2:
The patent integrates multiple functions into the FPGA fabric including configuration bit storage, logic functionality, and interconnect routing. The non-volatile memory cells are embedded within the reconfigurable logic blocks, allowing the same hardware resources to serve multiple purposes and reduce overall system complexity.
2Duration of action of stationary object
If external non-volatile memory is used to store configuration bits, then non-volatile storage is achieved, but device complexity increases due to peripheral circuitry
Solution Approach 1:
The patent merges the non-volatile memory storage function with the FPGA fabric structure itself. The non-volatile memory cells are integrated within the reconfigurable logic blocks and interconnect resources, eliminating the need for separate external memory interfaces and reducing peripheral circuitry complexity.
Solution Approach 2:
The patent embeds non-volatile memory cells within the hierarchical structure of the FPGA fabric. The memory cells are nested within logic blocks, which are nested within larger functional units, creating a compact integrated structure that eliminates external memory requirements.
3Duration of action of stationary object
If Flash memory is used for configuration bits in small-scale technologies, then non-volatile storage is achieved, but scalability is limited due to additional circuitry
Solution Approach 1:
The patent implements non-volatile memory with different characteristics at different locations within the FPGA fabric. Configuration bits near I/O blocks have different access characteristics than those in the core logic areas, allowing optimization for specific applications while maintaining scalability across different process nodes.
Solution Approach 2:
The patent creates a dynamic reconfigurable system where the non-volatile memory configuration can be changed after fabrication. The ability to reprogram the FPGA fabric allows the device to adapt to different applications and scale across various technology nodes without being constrained by fixed Flash memory architecture.
4Speed
If SRAM is used to load configuration bits upon startup, then fast access is achieved, but security is compromised due to centralized storage
Solution Approach 1:
The patent segments the configuration bit storage across multiple distributed non-volatile memory locations within the FPGA fabric rather than using centralized external storage. Each logic block has its own embedded non-volatile memory cells, distributing the configuration data and improving security while maintaining fast local access.
Solution Approach 2:
The patent uses the FPGA fabric itself as an intermediary between the non-volatile memory cells and the logic functionality. The reconfigurable logic blocks directly access their embedded non-volatile memory cells without requiring external memory interfaces, providing both security and fast access.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves security and reduces circuitry complexity, enabling scalable non-volatile memory in smaller-scale FPGAs without the need for external storage, thus enhancing performance and reducing boot time.
Implementation Method 1
a first resistive element and a second resistive element of the first group of resistive elements have a first resistivity and a second resistivity, respectively
Implementation Method 2
applying a voltage across the configuration bit to program or read the value stored by the configuration bit
Data Source
AI summary
The present disclosure is drawn to, among other things, a configuration bit including at least four resistive elements and a voltage amplifier. At least two first resistive elements may be electrically connected in series via a first electrode and at least two second resistive elements may be electrically connected in series via a second electrode. The at least two first resistive elements may be electrically connected in parallel to the at least two second resistive elements via a third electrode and a fourth electrode. The first electrode and the second electrode may be electrically connected to a voltage supply. The third electrode and the fourth electrode may be electrically connected to an input of the voltage amplifier.