FPGA Configuration Watermarking with Auxiliary Memory Cells
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Solution Overview
Problem
Existing FPGA devices and other digital logic devices face challenges in distinguishing between devices based on similar intellectual property designs, leading to difficulties in verifying the configuration version of a particular device.
Innovation Solution
A computer-implemented method and device architecture that incorporates a memory bus with addressable programme and auxiliary memory cells, allowing for the generation of a checksum value and a digital value that, when applied to a package checksum, produces a result complying with a predefined rule, thereby defining an augmented digital definition that includes auxiliary memory cells for watermarking or versioning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGAs are configured with programmable logic blocks and routing areas to implement various functions, then the adaptability and versatility of the device is improved, but the difficulty of detecting and measuring the specific configuration version worsens
Solution Approach 1:
The patent applies preliminary action by embedding a unique identifier directly into the configuration data before it is loaded into the FPGA. This identifier is prepared in advance during the configuration generation process, allowing the device to carry its own version information without requiring external tracking systems or complex measurement procedures during operation.
Solution Approach 2:
The patent uses copying by embedding a digital representation (unique identifier) of the configuration version directly into the FPGA's configuration memory. This creates a copy of the version information within the device itself, making it easily detectable and measurable without requiring physical inspection or complex external verification systems.
2Device complexity
If multiple logic blocks are interconnected through programmable routing areas to implement complex functions, then the device complexity increases, but the ease of operation for verifying configuration versions decreases
Solution Approach 1:
The patent extracts the version verification problem from the complex interconnection structure by embedding a dedicated unique identifier within the configuration data. This separates the verification function from the complex routing and logic block interconnections, making it possible to verify configuration versions through a simple, direct method independent of the device's internal complexity.
Solution Approach 2:
The unique identifier serves multiple functions simultaneously: it acts as a configuration version tag, a device fingerprint for identification, and a verification mechanism. This multi-functional approach simplifies operation by providing a single data element that handles multiple verification and identification tasks that would otherwise require separate complex procedures.
Data Source
AI summary
A method of defining a logic device is provided wherein the definition incorporates the definition of special auxiliary memory cells reserved for the presentation of a special code, incorporating a signature of the definition as a whole so as to constitute a watermark securing the design as a whole, and possibly other information. In certain embodiments, the special code may incorporate recursive signatures from preceding versions of the same device to as to constitute a watermark blockchain. A LUT based FPGA architecture is proposed with special addressable memory cells reserved for this purpose, wherein case a programming bitstream may constitute a definition in accordance with the inventive method.