Dynamic FPGA Container Reconfiguration with Local Block RAM Images

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Solution Overview

Problem

The time required for downloading and configuring partial reconfiguration in Field Programmable Gate Arrays (FPGAs) is too long, limiting the use of Dynamic Partial Reconfiguration (DPR) in projects.

Innovation Solution

Utilizing Block RAM (BRAM) to store configuration data independently from Configuration RAM (CRAM), allowing for direct linking between BRAM and CRAM to enable fast reconfiguration by using images stored locally, thereby reducing the need for external data transfer during runtime.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If configuration data is downloaded from external interfaces during runtime, then the FPGA can be reconfigured with new hardware applications, but the reconfiguration time becomes too long for practical use

Engineering Contradiction:
Improvereconfiguration capabilityVSAvoidreconfiguration time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

Configuration images are pre-loaded into the Block RAM of the FPGA before runtime operations begin. This preliminary action ensures that when reconfiguration is needed, the configuration data is already available in fast internal memory, eliminating the time-consuming external download process and enabling rapid switching between hardware applications.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The Block RAM serves as an intermediary storage element between the external configuration interface and the Configuration RAM. By using Block RAM as a buffer, the system can prepare configuration images in advance and transfer them to CRAM during runtime without blocking the operation of other FPGA logic, thus reducing reconfiguration time.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If Block RAM is used to store configuration images, then reconfiguration speed improves, but the available memory for data processing decreases

Engineering Contradiction:
Improvereconfiguration speedVSAvoidavailable memory
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The system dynamically allocates Block RAM resources between configuration storage and data processing based on runtime needs. When reconfiguration is not active, Block RAM can be used for data processing; when reconfiguration is needed, the pre-loaded images in Block RAM are quickly transferred to CRAM, freeing Block RAM for data processing operations. This dynamic allocation maximizes the utility of limited memory resources.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Instead of loading entire configuration images into Block RAM at once, the system loads only the necessary portions or uses compression techniques to store configuration data more efficiently. This partial loading approach reduces the memory footprint required for configuration storage while still enabling fast reconfiguration when needed.

Inventive Principle:
Principle #16Partial or excessive action

3Quantity of substance

If configuration data is stored in external components, then memory capacity is sufficient, but data transfer overhead increases power consumption and bus traffic

Engineering Contradiction:
Improveconfiguration storage capacityVSAvoidpower consumption
Core Design Contradiction:
Quantity of substanceVSLoss of energy

Solution Approach 1:

The invention merges the configuration storage function with the existing Block RAM resources already present in the FPGA. By combining the configuration storage role with the data processing memory, the system eliminates the need for separate external configuration memory components and their associated interfaces, thereby reducing power consumption and bus traffic while maintaining sufficient storage capacity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP4610838A1Dynamic partial FPGA reconfiguration
Publication Date: 2025.09.03 SIEMENS AG
  • EP4610838A1 patent drawingFigure 1~2
  • EP4610838A1 patent drawing

AI summary

Present invention concerns a Field Programmable Gate Array (100, 200), FPGA, the FPGA comprising: Block RAM (250); a plurality of configurable logic elements; and a container (160, 280). The container (160, 280) comprises a predetermined subset of said logic elements; such that a configuration of elements in the container (160, 280) may be changed independently from a configuration of logic elements outside the container (160, 280). It is proposed to store an image (A-D) in said block RAM (250), the image (A-D) comprising predetermined configuration data for said container (160, 280). Then, said container (160, 280) may be dynamically reconfigured based on the image (A-D). The invention also concerns a method for operating an FPGA, a computer program product and a storage medium.