FPGA CPU Clock Signal Stability Monitoring
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Solution Overview
Problem
In systems that include both FPGA and CPU, the instability of the clock signal outputted by the CPU after startup can prevent normal operation, as existing technologies do not effectively address this issue.
Innovation Solution
An information processing device comprising an FPGA, a CPU, a configuration execution unit, a clock signal monitoring unit, and a startup processing unit, where the clock signal monitoring unit detects stability of the clock signal from the CPU and the startup processing unit initiates startup only when the signal is stable, ensuring stable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the CPU is started up immediately after FPGA configuration is complete, then the startup process is faster, but the clock signal may be unstable causing system failure
Solution Approach 1:
The patent applies preliminary action by checking the stability of the clock signal output from the CPU before proceeding with the startup process. The control circuit monitors whether the clock signal has reached a stable state, and only after confirmation does it allow the startup sequence to continue. This prevents premature startup that would cause instability while minimizing the delay by immediately beginning the stability check upon configuration completion.
2Reliability
If the clock signal stability is monitored before startup, then the system startup reliability is improved, but the startup process becomes more complex
Solution Approach 1:
The patent introduces an intermediary control circuit that acts as a mediator between the CPU and the startup process. This control circuit specifically monitors the clock signal stability and uses it as a gatekeeping mechanism - the startup sequence is enabled only when the clock signal meets stability criteria. This intermediary component adds minimal complexity while ensuring reliable startup by decoupling the configuration completion event from the actual startup execution.
Data Source
AI summary
An objective is to provide an information processing device that can be started up stably, and an information processing method. A configuration execution unit of an information processing device writes configuration data into an FPGA. A clock signal monitoring unit detects whether a clock signal supplied from a CPU to the FPGA is stable or not, on condition that a configuration is complete. A startup processing unit starts up the CPU and the FPGA on condition that the clock signal is stable.