Heterogeneous Processor Object Detection via FPGA Feature Extraction
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Solution Overview
Problem
Current object detection algorithms face challenges in achieving a balance between performance and speed, particularly due to high computational demands and inefficiencies when processed on traditional CPU architectures, leading to slower computation speeds.
Innovation Solution
A heterogeneous processor system is introduced, comprising a processing unit and a programmable logic unit, where feature extraction is performed by the programmable logic unit and object detection is conducted by the processing unit, utilizing techniques like Aggregated Channel Features (ACF) extraction and Histogram of Oriented Gradient (HOG) to improve computational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If object detection algorithm is processed on traditional CPU architecture, then detection accuracy can be maintained, but computation speed becomes slow due to huge calculation amount
Solution Approach 1:
The patent segments the object detection algorithm into two distinct parts: feature extraction (handled by FPGA) and target detection (handled by CPU). This segmentation allows each component to be optimized for its specific function, with the FPGA performing parallel feature extraction operations while the CPU focuses on detection logic, thereby resolving the contradiction between maintaining detection accuracy and improving computation speed.
Solution Approach 2:
The patent introduces an intermediary mechanism (memory interface and data transfer protocol) between the FPGA and CPU that enables efficient exchange of feature data. This intermediary allows the FPGA to pre-process and store extracted features in memory, which the CPU then retrieves for detection, eliminating the bottleneck of real-time computation on the CPU while maintaining accurate detection results.
2Measurement precision
If more computational resources are allocated to improve detection performance, then detection accuracy improves, but system complexity and processing time increase
Solution Approach 1:
By segmenting the detection system into specialized FPGA and CPU components, the patent distributes computational resources according to function rather than concentrating all resources in a single complex processor. The FPGA handles computationally intensive feature extraction with parallel processing, while the CPU manages detection logic, reducing the complexity burden on any single component while improving overall detection performance.
3Ease of manufacture
If feature extraction and detection are performed sequentially on a single processor, then implementation is simple, but processing efficiency is low
Solution Approach 1:
The patent implements segmentation by physically separating feature extraction and detection functions into different hardware components (FPGA and CPU). This allows both operations to execute simultaneously in parallel, dramatically improving processing efficiency compared to sequential execution on a single processor, while the modular design keeps implementation manageable through clear interface definitions.
Solution Approach 2:
The FPGA performs preliminary feature extraction and stores results in memory before the CPU begins detection processing. This preliminary action by the FPGA prepares data in advance, allowing the CPU to immediately process extracted features without waiting for computation completion, thereby enabling parallel execution and improving overall processing efficiency.
Data Source
AI summary
The present disclosure provides an object detection method and an object detection device. The object detection device includes: a heterogeneous processor and a memory, the heterogeneous processor including: a processing unit and a programmable logic unit, wherein the programmable logic unit is configured to receive a to-be-detected image, perform feature extraction on the to-be-detected image, and write an extracted feature into the memory; the processing unit is configured to read the feature from the memory, perform target object detection according to the feature, and output a detection result to the programmable logic unit; and the programmable logic unit is further configured to receive the detection result, generate prompt information according to the detection result, and output the prompt information.