FPGA Configuration CRC Authentication for Safe Logic Activation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current SRAM-based FPGAs lack a method to ensure that a specific, approved configuration is used, and the configuration memory can be corrupted, posing risks in safety-critical systems.

Innovation Solution

Implement a method involving a memory module, comparator module, and interlock device to authenticate and enable only valid configurations by computing CRC checksums on the actual configuration memory post-loading, ensuring identical checksums before enabling logic functions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If SRAM-based FPGA is used for safety-critical systems, then adaptability and reconfigurability are improved, but configuration corruption risk and reliability deteriorate

Engineering Contradiction:
ImprovereconfigurabilityVSAvoidconfiguration corruption risk
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent performs CRC authentication of the configuration memory contents immediately after configuration loading but before enabling the logic functions. This preliminary verification ensures that any corruption is detected before it can affect system operation, resolving the contradiction by maintaining reconfigurability while preventing corrupted configurations from executing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements a feedback mechanism where the CRC authentication result controls an interlock signal that enables or disables the logic function outputs. If authentication fails, the interlock prevents output signals from being generated, creating a closed-loop safety mechanism that maintains reliability while preserving the reconfigurable nature of the FPGA.

Inventive Principle:
Principle #23Feedback

2Reliability

If configuration authentication is implemented, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improveconfiguration authenticationVSAvoidauthentication mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary authentication mechanism that sits between the configuration memory and the logic function outputs. The CRC authentication logic and interlock device act as mediators that verify configuration integrity without requiring fundamental changes to the FPGA architecture, thus improving reliability while limiting the increase in complexity to specific authentication components rather than the entire system.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If CRC authentication is performed on configuration memory, then configuration integrity is improved, but processing time increases

Engineering Contradiction:
Improveconfiguration integrityVSAvoidauthentication processing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs the CRC authentication as a preliminary step during the configuration loading process, before the FPGA begins normal operation. By completing the authentication check during the initial configuration phase rather than during runtime, the patent ensures configuration integrity while minimizing the impact on operational processing time.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3989090B1Configuration authentication prior to enabling activation of a FPGA having volatile configuration-memory
Publication Date: 2025.12.03 KONGSBERG DEFENCE & AEROSPACE
  • EP3989090B1 patent drawingFigure 1~2
  • EP3989090B1 patent drawingFigure 3
  • EP3989090B1 patent drawingFigure 4~6

AI summary

A method and system for authenticating and enabling activation of a configuration used for controlling a product, where the configuration is implemented as safety critical logic functions in programmable logic blocks of a Field Programmable Gate Array, FPGA, having a volatile configuration-memory. The configuration is loaded into the volatile configuration-memory of the FPGA via an external interface input of the FPGA. The content of the configuration-memory of the FPGA is read via an interface of the FPGA. This is done immediately after completed loading of the configuration into the memory of the FPGA. A Cyclic Redundancy Check, CRC, checksum of the read content of the configuration-memory is computed in an CRC checksum generator, and a resulting generated CRC checksum value is compared with an externally stored valid CRC checksum value of the expected FPGA configuration. It is then checked if the generated CRC checksum value and the stored valid CRC checksum value match and the outputs of selected logic functions of the FPGA are enabled only if the generated CRC check value and the stored valid CRC checksum values match.