On-Chip Critical Path Test Circuit for FPGA Timing Verification
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Solution Overview
Problem
Testing the functionality of designs implemented in partially programmable Field-Programmable Gate Arrays (FPGAs) is challenging due to their partial programmability, which complicates the verification of critical paths and timing constraints.
Innovation Solution
A test circuit is introduced that includes a sequence generator, source and destination sequential circuits, an analyzer circuit, and a controller circuit to verify the critical path by generating data signals and measuring timing from the source sequential circuit to a clock enable pin or set/reset pin of the destination sequential circuit, allowing for on-chip verification of critical paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a test circuit is added to verify critical paths in partially programmable FPGAs, then the ability to verify timing constraints is improved, but the device complexity increases
Solution Approach 1:
The test circuit is nested within the existing FPGA fabric structure, utilizing the programmable logic resources already present in the device. The sequence generator, source sequential circuit, destination sequential circuit, and analyzer circuit are all implemented using the FPGA's programmable logic blocks, allowing the test functionality to be integrated without adding external components.
Solution Approach 2:
The test circuit components are designed to utilize the universal programmable logic resources of the FPGA. The sequence generator can generate various test patterns, the sequential circuits can be configured for different timing measurements, and the analyzer circuit can verify multiple timing constraints, making the test circuit adaptable to different verification needs within the same hardware platform.
2Measurement precision
If on-chip test circuitry is implemented for critical path verification, then the measurement precision of timing constraints is improved, but the area occupied on the chip increases
Solution Approach 1:
The test circuit is implemented locally within the critical path being tested, using the programmable logic blocks that already constitute the critical path itself. The source sequential circuit is placed at the input of the critical path, the destination sequential circuit at the output, and the analyzer circuit is integrated within the same logic fabric, minimizing additional area occupation while enabling precise local timing measurements.
Data Source
AI summary
A test circuit in an integrated circuit (200 or 300) is used for verifying a critical path of a circuit (230) under test. The test circuit can include a sequence generator (202) generating a data signal for the critical path, a source sequential circuit (208) for receiving the data signal coupled to an input of the critical path, a destination sequential circuit (210 or 310) for receiving an output of the critical path, and an analyzer circuit (212 or 312) for verification of timing of the critical path by measuring timing from the source sequential circuit to a clock enable pin (209) or a set/reset pin (309) of the destination sequential circuit. The test circuit can further include a controller circuit (220) for strobing a comparison circuit (218) in the analyzer circuit at a predetermined clock time. The integrated circuit can be part of an FPGA or FPGA fabric.