FPGA Cryptographic Combiner for Side Channel Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional cryptographic methods are vulnerable to side channel attacks, such as differential power analysis (DPA), due to information leakage through power consumption during cryptographic processing, which compromises the security of secret values.
Innovation Solution
A high-speed cryptographic combining method that uses modern electronic processors with dedicated computational circuits to mix large bit-length inputs within a single clock cycle, minimizing side channel leakage by employing a network of look-up tables (LUTs) and programmable logic devices (PLDs) to transform input values into output values efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional cryptographic methods process secret key data and input information data by combining byte pairs across multiple clock cycles with intermediate register storage, then the processing can be implemented using standard processor architecture, but power consumption during register writes leaks information about secret values through side channels
Solution Approach 1:
The patent divides the secret key data and input information data into multiple 8-byte segments (e.g., 16 segments for 128-bit data). Each segment is processed through separate combining operations using dedicated combin er circuits, allowing the processing to be distributed across parallel paths rather than sequential register operations, thereby reducing side channel leakage from intermediate storage
Solution Approach 2:
The patent introduces dedicated combiner circuits that directly combine segmented key data and input data without requiring intermediate register storage. These combiner circuits act as intermediaries that perform the combining function in a way that minimizes power consumption variations, eliminating the need for vulnerable register write operations during the combining process
2Productivity
If cryptographic combining functions are implemented by splitting input quantities into small packets and combining them serially or in parallel across processor real estate, then the implementation can use conventional processor architecture, but the processing speed is limited by the need to store intermediate values and await further processing
Solution Approach 1:
The patent merges multiple combining operations into a unified hardware structure where segmented key data and input data are combined through a network of dedicated combiner circuits. This merging allows all segment combinations to occur simultaneously in a single clock cycle, achieving high-speed processing while managing complexity through structured circuit design
Solution Approach 2:
The patent transitions from sequential processing (one combination at a time) to parallel processing across multiple dimensions by distributing the combining operations across multiple combiner circuits that operate simultaneously. This dimensional expansion from time-sequential to space-parallel processing dramatically increases throughput
Data Source
AI summary
A system, apparatus, method, and/or computer program product is disclosed for decreasing side channel signal leakage and increasing speed of cryptographic combining operations. An exemplary method may be incorporated, in an exemplary embodiment, in an exemplary programmable logic device (PLD) such as, e.g., but not limited to, a field programmable gate array (FPGA) implementation of at least one cryptographic combining process, or may include an application specific integrated circuit (ASIC) design where cryptographic combining with minimal side channel signal leakage and high speed are provided.