FPGA Data Masking Circuit With On-Chip Mask Generation
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Solution Overview
Problem
Current FPGA-based systems face inefficiencies in data masking operations for machine learning models, particularly in terms of memory storage, bandwidth, and arithmetic overhead, which hinder performance and increase energy consumption during training processes.
Innovation Solution
Implementing a data masking circuit on FPGAs that generates masks on-device without floating-point arithmetic, using a multiplexer to select between data values and alternative values based on mask data, and configuring the circuit to handle various mask types, including triangular masks, to reduce memory and bandwidth usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If data masking is performed using conventional software implementations on general purpose processors, then flexibility in handling different mask types is maintained, but computing time and energy consumption increase significantly
Solution Approach 1:
The patent replaces software-based data masking operations on general purpose processors with hardware-based masking circuits implemented on FPGAs. This substitution of mechanical/computational systems (software execution) with hardware circuits eliminates the need for complex software interpretation and reduces energy consumption by performing masking operations at the circuit level rather than through software instruction execution.
Solution Approach 2:
The patent changes the operational parameters of the masking operation by implementing dedicated hardware circuits that operate at fixed, optimized parameters for masking. The FPGA-based masking circuits use fixed-point arithmetic and dedicated logic paths with predetermined timing and voltage levels, contrasting with the variable parameters of software execution on general purpose processors.
2Measurement precision
If data masking is performed using floating-point arithmetic, then precision is maintained, but computational resources and memory overhead increase
Solution Approach 1:
The patent employs fixed-point arithmetic instead of floating-point arithmetic for masking operations. Fixed-point numbers use simpler binary representations without exponent fields, requiring less memory storage. The masking circuits use integer-based fixed-point operations that consume fewer computational resources while maintaining sufficient precision for the masking application, where extreme numerical precision is not critical.
Solution Approach 2:
The patent extracts and removes the floating-point arithmetic unit from the masking circuit implementation. By eliminating the floating-point operation requirement, the design reduces memory overhead associated with storing and processing floating-point mask values and data, while still achieving effective masking through fixed-point arithmetic operations in the hardware circuit.
3Adaptability or versatility
If mask data is stored in external memory and transferred over communication buses, then flexibility in mask selection is maintained, but bandwidth consumption and transfer time increase
Solution Approach 1:
The patent implements mask generation logic nested within the FPGA device itself, allowing masks to be generated internally rather than being stored and transferred from external memory. The masking circuit includes integrated logic that can generate common mask patterns (such as triangular masks for autoregressive modeling) directly within the hardware, eliminating the need for external memory access and bus transfer for these standard mask types.
Solution Approach 2:
The patent implements preliminary mask generation capability within the FPGA, where masks can be pre-computed and loaded into on-chip block memory before processing begins. For recurring mask patterns, the hardware circuitry can generate masks in advance and store them in fast on-chip memory, avoiding real-time external memory access during critical processing phases and reducing bandwidth consumption.
4Speed
If general purpose processors are used for data masking, then reconfigurability is maintained, but computing speed and performance decrease
Solution Approach 1:
The patent leverages the dynamic reconfigurability of FPGAs, which allow the masking circuit hardware to be reprogrammed and reconfigured in the field without being locked into a fixed ASIC configuration. This dynamic aspect enables the same hardware to be adapted for different masking requirements and model architectures, maintaining versatility while achieving hardware-level performance speeds through dedicated logic paths and parallel processing capabilities.
Data Source
AI summary
A field programmable gate array (FPGA) including a configurable interconnect fabric connecting a plurality of logic blocks, the configurable interconnect fabric and the logic blocks being configured to implement a data masking circuit configured to: receive input data including data values at a plurality of indices of the input data; select between a data value of the data values and an alternative value using a masking multiplexer to generate masked data, the masking multiplexer being controlled by a mask value of a plurality of mask values at indices corresponding to the indices of the input data; and output the masked data. In some examples, the configurable interconnect fabric and the logic blocks are further configured to implement a mask generation circuit configured to generate the mask values. In some examples, the mask values are received from external memory.