FPGA DDR Memory Parallel Data Reading via Controller Segmentation
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Solution Overview
Problem
The existing methods for reading data from FPGA boards are inefficient and result in poor resource utilization, as the FPGA board reads data through its own DDR controllers while other DDR memories and controllers remain idle, leading to low data reading speed and suboptimal resource usage.
Innovation Solution
The method involves sending hardware information about the FPGA board to the host, performing data slice processing based on the available DDR memories, and transmitting each data slice to corresponding DDR spaces for parallel reading and calculation, utilizing multiple DDR controllers to enhance data reading efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is read through a single DDR controller on the FPGA board, then the reading process is simple to implement, but the data reading speed is low and resource utilization rate is poor
Solution Approach 1:
The patent divides the data reading process into multiple parallel channels by utilizing multiple DDR controllers simultaneously. Each controller reads data from its associated DDR memory independently, segmenting the monolithic reading task into concurrent sub-tasks that collectively achieve higher throughput
Solution Approach 2:
The patent combines multiple DDR controllers and their associated memory resources into a unified parallel reading system. By merging the capabilities of multiple controllers working simultaneously, the system achieves aggregate reading speed that exceeds single-controller operation
2Productivity
If multiple DDR controllers are utilized for parallel data reading, then data reading efficiency is improved, but the system complexity increases
Solution Approach 1:
The patent designs the FPGA board with multiple identical DDR controller modules that can be configured and activated based on data size requirements. This universal modular approach allows the system to scale from single to multi-controller operation, providing flexibility that manages complexity while maintaining high performance capability
Solution Approach 2:
The patent implements dynamic controller allocation where the number of active DDR controllers is adjusted according to the size of the data buffer and processing requirements. This dynamic adaptation optimizes resource utilization and balances performance gains against system complexity
3Productivity
If only one DDR controller is used for reading data, then the control logic is simple, but the resource utilization rate is poor
Solution Approach 1:
The patent segments the data buffer into multiple portions, each assigned to a specific DDR controller for parallel reading. This segmentation strategy ensures that multiple memory resources are actively utilized simultaneously, improving overall resource utilization while the segmentation logic remains manageable through systematic allocation
Data Source
AI summary
The method includes: an FPGA board feeds back the quantity of controllers and the total quantity of DDR memories after receiving a hardware information acquisition request from a host; after a data space application request is received from the host, on the basis of the data space application request, perform data slice processing on data to be calculated, wherein the data space application request carries the dedicated application space capacity of each DDR and the data to be calculated, and the total quantity of slices of the data to be calculated is the same as the total quantity of DDR memories; and transmit each sliced data to a corresponding DDR space, and according to a data storage position of the sliced data in each DDR, read the data from the DDR memory space in parallel by means of the plurality of controllers and calculate same.