Securing FPGA Debug Ports via Remote Access Controller

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Solution Overview

Problem

Current Information Handling Systems (IHSs) lack secure mechanisms to control access to Field Programmable Gate Array (FPGA) card debug ports, making them vulnerable to unauthorized access and potential malicious modifications.

Innovation Solution

A method and system that utilize a remote access controller to determine the status of the FPGA card debug port, generate a passcode by hashing the FPGA card's serial number with the IHS's service tag, and manage access through a sideband management bus, ensuring only authenticated administrators can access the debug port, which is disabled upon next power cycle.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If the debug port is left enabled for developer access, then ease of operation is improved, but security is worsened due to vulnerability to unauthorized access

Engineering Contradiction:
Improvedebug port accessibilityVSAvoidunauthorized access vulnerability
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The system performs preliminary actions by disabling the debug port at initialization and only enabling it temporarily when authentication is provided. The remote access controller proactively manages the debug port state based on authentication status, ensuring security is maintained while allowing access when needed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The remote access controller acts as an intermediary between authenticated users and the debug port. It receives authentication credentials, verifies them against stored passcodes, and controls the management controller to enable or disable the debug port accordingly. This intermediary layer prevents direct unauthorized access to the debug port.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If the debug port is disabled by default for security, then security is improved, but ease of operation is worsened due to restricted access

Engineering Contradiction:
Improveunauthorized access preventionVSAvoiddebug port accessibility
Core Design Contradiction:
Object-affected harmful factorsVSEase of operation

Solution Approach 1:

The system disables the debug port by default at initialization (preliminary action) and only enables it temporarily when authentication is provided. This ensures security is maintained while allowing access when needed through the authentication process.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The debug port state is dynamic rather than static. It transitions between disabled and enabled states based on authentication events. The remote access controller dynamically adjusts the debug port accessibility based on the authenticated user's credentials and the current system state.

Inventive Principle:
Principle #15Dynamics

3Object-affected harmful factors

If passcode generation uses hashing of serial number and service tag, then security is improved, but device complexity is worsened

Engineering Contradiction:
Improvepasscode securityVSAvoidaccess control mechanism
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The system changes parameters by using hashing of the FPGA card's serial number concatenated with the IHS's service tag to generate unique passcodes. This cryptographic transformation converts simple identifiers into secure authentication credentials, improving security while maintaining a relatively simple implementation approach.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10852352B2System and method to secure FPGA card debug ports
Publication Date: 2020.12.01 DELL PROD LP
  • US10852352B2 patent drawing
  • US10852352B2 patent drawing
  • US10852352B2 patent drawing

AI summary

Embodiments are described for securing access to a debug port of an FPGA (Field Programmable Gate Array) card installed within an IHS (Information Handling System). A remote access controller determines the status of the FPGA card debug port via a query to a management controller of the FPGA card. The remote access controller generates a passcode for the debug port and disables the debug port via a message to the management controller. The management controller detects a request, that includes a requestor password, for access to the debug port. The remote access controller authorizes the requestor's access to the debug port if the requestor password matches the generated passcode. The remote access controller disables the debug port upon each power cycle of the FPGA card or upon detecting removal of a device from the debug port.