Debugging Logic Placement in FPGA Emulation
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Solution Overview
Problem
Conventional emulation environments are inefficient in placing and routing debugging logic in field-programmable gate arrays (FPGAs), leading to suboptimal connections between debugging logic and logic components, which can result in non-compiling FPGAs or resource overloading.
Innovation Solution
A host system determines the placement and routing of debugging logic in FPGAs such that connections between debugging logic and logic components are optimized, prioritizing short distances and minimizing interference with existing logic component routings by placing debugging logic near logic components before or after their placement and routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If debugging logic is placed on FPGA without optimization, then debugging functionality is achieved, but routing efficiency deteriorates and resource overload occurs
Solution Approach 1:
The patent applies preliminary action by placing debugging logic units on the FPGA before placing the actual logic components. This advance placement allows the routing tool to optimize connections between debugging logic and logic components during the routing phase, rather than adding debugging logic afterward when routing resources are already consumed. The host system determines placements of debugging logic units first, then places logic components, and routes connections between them.
2Ease of operation
If debugging logic is placed after logic components, then logic component routing is established first, but debugging logic connections become long and inefficient
Solution Approach 1:
The patent reverses the conventional sequence by placing debugging logic units before logic components. This preliminary placement of debugging logic allows subsequent logic component placement and routing to naturally create shorter, more efficient connections to the debugging logic, rather than forcing long connections after logic components and their routes are already fixed.
3Adaptability or versatility
If debugging logic is placed without considering logic component locations, then placement flexibility is maintained, but routing optimization is lost
Solution Approach 1:
The patent maintains placement flexibility while achieving routing optimization by placing debugging logic units at predetermined locations before logic component placement. The host system determines these placements strategically, then uses this fixed debugging logic framework to guide subsequent logic component placement and routing, ensuring both adaptability and precision.
Data Source
AI summary
Embodiments relate an emulation environment that places debugging logic in a manner that connections between the debugging logic and logic components outputs can be efficiently routed. In one embodiment, the host system places the debugging logic after placing the logic components of the DUT, but before routing the logic components. In another embodiment, the host system places debugging logic after placing and routing logic components of the DUT. In another embodiment, for one or more emulator FPGAs, the host system places debugging logic units of the debugging logic evenly across the FPGA before placing logic components of the DUT.