FPGA Full-Path Circuit Delay Measurement Using Shadow Registers
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Solution Overview
Problem
Existing dynamic voltage scaling technologies for FPGAs are limited by the unpredictability of critical paths during design, leading to incomplete calibration and invalidation in varying operating conditions, which compromises circuit safety.
Innovation Solution
A full-path circuit delay measurement device for FPGAs utilizing two shadow registers and a phase-shifted clock, where the registers sample the clock edges to indirectly measure circuit delays by adjusting the phase difference between the clocks from 0° to 360°, ensuring real-time measurement across all conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If calibration table-based technique is used to measure circuit delay, then measurement can be performed offline, but it cannot cover all operating conditions and calibration information becomes invalid when operating environment differs from calibration environment
Solution Approach 1:
The patent transitions from static offline calibration to dynamic real-time measurement. The measurement device continuously monitors circuit delay during actual operation, adapting to changing operating conditions (voltage, temperature, frequency) without requiring recalibration. This dynamic approach ensures measurement validity across all operating environments.
Solution Approach 2:
The measurement device performs self-measurement by utilizing the circuit's own operating signals. The shadow registers sample the actual clock edges present during operation, and the phase difference detection automatically adapts to current operating conditions without external calibration input, making the system self-sufficient across varying environments.
2Reliability
If real-time delay measurement is implemented to ensure circuit safety under DVS, then operational reliability is improved, but device complexity increases due to additional measurement circuits
Solution Approach 1:
The patent uses shadow registers that replicate the functionality of the main clocking registers but are dedicated solely to measurement purposes. These shadow registers capture the same clock signals without interfering with normal circuit operation, providing a simplified measurement path that parallels the main data path.
Solution Approach 2:
The measurement device components serve multiple functions: the shadow registers both sample clock edges for delay measurement and maintain synchronization with the operating frequency. The phase difference detection mechanism simultaneously measures delay and adapts to frequency changes, reducing the need for separate dedicated circuits for each function.
3Adaptability or versatility
If phase-shifted clock sampling method is used, then all path types can be measured at all voltages and frequencies, but the measurement system requires adjustable phase difference capability
Solution Approach 1:
The patent employs periodic phase shifting of the sampling clock, systematically varying the phase difference in discrete steps (e.g., 0°, 45°, 90°, 135°, 180°, 225°, 270°, 315°). This periodic phase modulation allows comprehensive coverage of all possible signal transitions without requiring continuous phase adjustment, simplifying the control mechanism while maintaining full measurement capability.
Solution Approach 2:
The measurement system dynamically adjusts the sampling clock phase based on detected signal transitions. When a transition is detected, the system automatically shifts phase to capture the next transition, adapting in real-time to varying operating conditions without manual intervention or complex pre-programming.
Data Source
AI summary
A full-path circuit delay measurement device for a field-programmable gate array (FPGA) and a measurement method are provided. The measurement device includes two shadow registers and a phase-shifted clock, where the two shadow registers take an output of a measured combinational logic circuit as a clock and sample the phase-shifted clock SCLK as data; the two shadow registers are respectively triggered on rising and falling edges of the output of the measured combinational logic circuit to sample the phase-shifted clock; outputs of the two shadow registers are delivered by an OR gate as an input into a synchronization register; a clock of the synchronization register serves as a clock MCLK of the measured combinational logic circuit; an output of the synchronization register serves as that of the circuit delay measurement device; the phase-shifted clock SCLK and the clock MCLK of the measured combinational logic circuit have the same frequency.