FPGA Diagnostic Testing for Safety Critical Systems
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Solution Overview
Problem
Conventional diagnostic testing methods for FPGAs in safety-critical systems, such as autonomous driving and IoT applications, are time-consuming, require frequent changes, and lack quantifiable diagnostic coverage, making them inefficient for meeting Automotive Safety Integrity Level (ASIL) requirements.
Innovation Solution
The implementation of Design For Test (DFT) methodologies combined with FPGA-specific enhancements allows for the creation of quantifiable safety diagnostic solutions, enabling diagnostic checks without exposing proprietary test methods, and enabling testing during runtime to meet key-on/key-off diagnostic requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual examination or application specific diagnostics are used for FPGA testing, then diagnostic coverage can be achieved, but the implementation time increases and diagnostic coverage becomes hard to measure
Solution Approach 1:
The patent changes the parameter of diagnostic testing from manual/examination-based to automated/runtime-based. By implementing diagnostic testing during FPGA runtime operation rather than during manual examination phases, the system achieves measurable diagnostic coverage while reducing implementation time. The runtime diagnostic capability allows continuous monitoring without interrupting normal operation.
Solution Approach 2:
The patent enables the FPGA system to perform self-diagnosis during runtime. The diagnostic testing is integrated into the normal operation flow, allowing the system to monitor and test itself automatically without requiring external manual intervention. This self-service approach reduces implementation time while maintaining diagnostic coverage.
2Reliability
If application specific diagnostics are designed for each FPGA implementation, then diagnostic coverage can be achieved, but the solution requires frequent changes and is hard to measure
Solution Approach 1:
The patent implements a universal diagnostic testing framework that can be applied across different FPGA implementations without requiring application-specific customization. The runtime diagnostic capability serves multiple functions: it tests various FPGA components, monitors different operational states, and provides measurable coverage metrics. This multi-functional approach reduces device complexity by eliminating the need for separate diagnostic solutions for each application.
Solution Approach 2:
The patent focuses diagnostic testing on critical FPGA components and runtime operations rather than attempting to test every possible function. By concentrating diagnostic resources on the most important areas (partial action), the system achieves measurable diagnostic coverage without the complexity of comprehensive application-specific diagnostics. The approach tests sufficient functionality to ensure safety without over-engineering the diagnostic solution.
3Reliability
If conventional diagnostic testing methods are used, then testing can be performed, but the time to develop diagnostic solutions increases and ASIL requirements are difficult to meet
Solution Approach 1:
The patent incorporates diagnostic testing capabilities into the FPGA design and configuration process in advance. By preparing the diagnostic infrastructure during the design phase and configuring it alongside the main FPGA functionality, the system is ready for immediate runtime testing without requiring separate development cycles. This preliminary action accelerates the overall development of diagnostic solutions while ensuring ASIL compliance.
Solution Approach 2:
The patent enables continuous diagnostic testing during FPGA runtime operation. Rather than performing discrete testing phases that interrupt development, the system continuously monitors and tests critical functions throughout operation. This continuous action provides ongoing verification of ASIL requirements while maintaining productivity, as the diagnostic process runs concurrently with normal system operation rather than requiring separate development time.
Data Source
AI summary
Methods and apparatus relating to diagnostic testing of FPGAs for safety critical systems are described. In an embodiment, logic circuitry (e.g., a processor) performs one or more diagnostic operations on a portion of a Field Programmable Gate Array (FPGA) based on one or more test vectors. Memory stores the one or more test vectors. The logic circuitry performs the one or more diagnostic operations on the portion of the FPGA during runtime. Other embodiments are also disclosed and claimed.