Cache Coherent FPGA Tracking Dirty Cache Lines for VM Live Migration
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Solution Overview
Problem
The existing live migration of virtual machines is inefficient due to time-consuming handling of write page faults, unnecessary copying of entire pages, and frequent pausing and resuming of virtual machines, which leads to resource wastage and performance degradation.
Innovation Solution
Employing cache coherent FPGAs to track and copy dirty cache lines instead of entire pages, aggregating them into pages for efficient transfer during live migration, thereby reducing the need for page faults and minimizing data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If write page faults are handled by protecting memory pages and catching page faults, then dirty pages can be tracked, but the process becomes time consuming and inefficient
Solution Approach 1:
The patent replaces the software-based page fault handling mechanism with a hardware-based cache coherence monitoring mechanism using FPGAs. The FPGA directly monitors cache coherence events (such as writebacks) to identify dirty cache lines, eliminating the need for software page fault traps and handlers. This hardware-based approach provides both accurate tracking and reduced time overhead.
Solution Approach 2:
The patent introduces an intermediary FPGA component that sits between the source host's memory system and the migration process. This FPGA acts as a monitoring intermediary that observes cache coherence events and identifies dirty cache lines without interfering with normal VM operation, thereby enabling efficient tracking without page faults.
2Reliability
If entire memory pages are copied to the destination host, then all modified data is transferred, but resources are wasted when only a small portion of the page is modified
Solution Approach 1:
The patent segments the memory transfer unit from the traditional page level down to the cache line level. By monitoring individual cache lines for dirtiness and only copying those that have been modified, the system transfers only the necessary portions of memory rather than entire pages. This segmentation enables precise tracking and minimal data transfer while maintaining data completeness.
Solution Approach 2:
The patent applies local quality by treating different cache lines within the same memory page differently based on their actual modification status. Instead of uniformly copying entire pages, the system identifies and copies only the specific cache lines that have been dirtied, allocating bandwidth resources efficiently based on local modification needs rather than global page-level assumptions.
3Measurement precision
If memory pages are tracked by write protection and page fault catching, then dirty pages are identified, but the operation slows down live migration
Solution Approach 1:
The patent replaces the software-based page fault detection mechanism with a hardware-based cache coherence monitoring system using FPGAs. The FPGA directly monitors hardware cache events to identify dirty cache lines in real-time without requiring VM pauses or page fault traps, thereby maintaining both detection accuracy and migration speed.
Solution Approach 2:
The patent enables continuous monitoring of cache coherence events throughout the live migration process without interrupting VM execution. The FPGA continuously tracks dirty cache lines as the VM runs, eliminating the need to pause the VM for detection, thus maintaining continuous productive action while accurately identifying dirty data.
4Productivity
If the virtual machine is paused to copy remaining dirty pages, then migration can be completed, but performance degradation occurs during pausing
Solution Approach 1:
The patent segments the migration process into continuous dirty cache line tracking that occurs during VM execution, eliminating the need for complete VM pausing. By tracking at the cache line level continuously, the system can identify and transfer dirty data incrementally without stopping the VM, thereby completing migration with minimal or no downtime.
Solution Approach 2:
The patent maintains continuous useful action by allowing the VM to remain running throughout the migration process while the FPGA continuously monitors and tracks dirty cache lines. This continuous operation eliminates the need to pause the VM for migration operations, maintaining both migration progress and VM performance simultaneously.
Data Source
AI summary
A virtual machine running on a source host is live migrated to a destination host. The source host includes a first processing node with a first processing hardware and a first memory, and a second processing node with a second processing hardware and a second memory. While the virtual machine is running on the first processing hardware, the second processing hardware tracks cache lines of the first processing hardware that become dirty as a result of write operations performed on one or more memory pages of the virtual machine. The dirty cache lines are copied to the destination host in units of a cache line or groups of cache lines.