FPGA DNN Inference via Dynamic Precision Bitstream Partitioning
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Solution Overview
Problem
Current deep neural network (DNN) inference on field programmable gate arrays (FPGAs) lacks flexibility and efficiency in reconfiguring logic functions, leading to suboptimal performance and long response times, especially when dealing with varying workloads and precision requirements.
Innovation Solution
The method involves dynamically reconfiguring FPGAs by partitioning them into sub-regions with different precision configurations, allowing for the creation of bitstream files that can be used to adjust precision settings in real-time, enabling efficient inference and minimizing end-to-end response time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGAs are reconfigured for different logic functions, then adaptability is improved, but reconfiguration time increases
Solution Approach 1:
The FPGA is divided into multiple sub-regions, each capable of being independently configured for different precision requirements. This segmentation allows selective reconfiguration of only the necessary sub-regions rather than the entire FPGA, thereby reducing overall reconfiguration time while maintaining adaptability.
Solution Approach 2:
Multiple bitstream files corresponding to different precision configurations are pre-generated and stored before runtime. When inference needs to switch between different precision levels, the system can directly load the pre-prepared bitstream file without performing full reconfiguration, significantly reducing reconfiguration time.
2Productivity
If precision configurations are optimized for specific workloads, then inference performance is improved, but device complexity increases
Solution Approach 1:
The FPGA is designed with multi-functionality to support multiple precision configurations (e.g., different number representations such as binary32, binary16, binary8, binary4) within the same hardware platform. By making the device universal and capable of handling various precision requirements, it eliminates the need for separate specialized devices for each precision level, thus improving inference performance across different workloads without proportionally increasing device complexity.
Solution Approach 2:
The system optimizes inference performance by dynamically changing parameters such as precision configuration and number representation based on the specific workload requirements. Different sub-regions can be configured with appropriate precision levels (e.g., high precision for critical calculations, lower precision for less critical operations), allowing the device to adapt its parameters to maximize performance for each inference task.
Data Source
AI summary
A field programmable gate array (FPGA) may be used for inference of a trained deep neural network (DNN). The trained DNN may comprise a set of parameters and the FPGA may have a first precision configuration defining first number representations of the set of parameters. The FPGA may determine different precision configurations of the trained DNN. A precision configuration of the precision configurations may define second number representations of a subset of the set of parameters. For each precision configuration of the determined precision configurations a bitstream file may be provided. The bitstream files may be stored so that the FPGA may be programmed using one of the stored bitstream files for inference of the trained DNN.