FPGA Dynamic Region Allocation for Acceleration Resource Utilization
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Solution Overview
Problem
Existing network functions virtualization (NFV) systems face challenges in optimizing FPGA utilization due to limited area division and static allocation of acceleration functions, leading to inefficient use of hardware resources.
Innovation Solution
A method and device that combines multiple acceleration applications into a single combined application, which is then burned to an acceleration resource, allowing for improved resource utilization through dynamic allocation and migration, thereby enhancing the utilization of existing FPGAs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If area division is performed in the FPGA to enable partial reconfiguration, then adaptability to meet new requirements is improved, but the quantity of areas is limited and area size cannot be dynamically adjusted, leading to inefficient resource utilization
Solution Approach 1:
The patent divides the FPGA into multiple dynamic regions that can be flexibly segmented and reconfigured. Instead of fixed area division, the system creates可变的 regional segments that can be dynamically adjusted in size and position to match the specific requirements of different acceleration applications, thereby improving both adaptability and resource utilization efficiency
Solution Approach 2:
The patent implements dynamic region allocation where the size, shape, and position of FPGA regions can be adjusted in real-time based on application requirements. This dynamic approach replaces the static area division with flexible, on-demand region creation and merging, allowing optimal resource utilization while maintaining high adaptability to different acceleration needs
2Ease of operation
If multiple acceleration applications are allocated to separate acceleration resources, then each application can be independently managed, but the number of FPGAs increases and resource utilization efficiency decreases
Solution Approach 1:
The patent merges multiple acceleration applications into a single FPGA by implementing dynamic region allocation. Different applications are assigned to different dynamic regions within the same FPGA, allowing multiple applications to coexist and be independently managed while reducing the total number of FPGAs required
Solution Approach 2:
The patent makes a single FPGA universal by enabling it to host multiple different acceleration applications simultaneously through dynamic region configuration. The FPGA can dynamically allocate different regions to different applications based on demand, achieving multi-functionality while reducing hardware quantity
3Ease of manufacture
If a single acceleration application is burnt to an acceleration resource, then the resource allocation is simple, but the resource utilization is low and cannot meet varying requirements
Solution Approach 1:
The patent implements dynamic region allocation that allows acceleration resources to be flexibly reconfigured based on application requirements. Instead of static one-to-one mapping, the system can dynamically create, merge, and split regions to match the specific needs of different applications, maintaining simple allocation processes while achieving high adaptability
Data Source
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AI summary
This application provides an acceleration processing method and device. In the acceleration processing method, an acceleration processing device combines a first acceleration application and a second acceleration application to obtain a first combined application, and burns the first combined application to a first acceleration resource, where the first combined application includes a top module, the first acceleration application, and the second acceleration application, and the top module includes a statement used to invoke the first acceleration application and a statement used to invoke the second acceleration application. Solutions provided in this application help improve acceleration resource utilization.