FPGA ECC Register Protection for Real-Time SEU Correction
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Solution Overview
Problem
Current FPGA technologies in aerospace engineering face limitations in error correction reliability and circuit area integration due to the spatial energetic particle-induced single event upset (SEU) problem, where existing methods like triple module redundant (TMR) are inefficient and require significant circuit space.
Innovation Solution
An FPGA with an automatic error detection and correction function for programmable logic modules, incorporating a check code generation circuit, check code registers, a check circuit, decoding circuit, and trigger circuit that uses ECC encoding and Hamming codes to detect and correct errors in real-time, reducing circuit area requirements and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TMR method is used for error correction in configuration memory, then reliability is improved, but circuit area increases significantly
Solution Approach 1:
The patent uses ECC encoding to create compact redundant information (check codes) that is much smaller than the full TMR approach. Instead of copying entire registers three times, the system generates concise check codes that can detect and correct errors with minimal area overhead.
Solution Approach 2:
The patent changes the error correction approach from spatial redundancy (TMR's three-fold copying) to information-theoretic redundancy (ECC's check codes). This parameter change in the correction methodology achieves comparable reliability with dramatically reduced circuit area.
2Reliability
If TMR method is applied to all registers in configuration memory, then error protection is improved, but device complexity increases
Solution Approach 1:
The patent segments the error protection function into a dedicated error checking and correction device that operates independently from the main logic. This segmentation allows the protection mechanism to be applied selectively to configuration memory without complicating the entire device architecture.
Solution Approach 2:
The patent introduces an intermediary error checking and correction device that sits between the configuration memory and the programmable logic modules. This intermediary handles all error detection and correction operations, simplifying the design by centralizing the protection function rather than embedding it in every register.
3Reliability
If real-time error detection and correction is implemented in programmable logic modules, then reliability is improved, but circuit area increases
Solution Approach 1:
The patent merges the error checking and correction functionality into a dedicated device that works in tandem with the programmable logic modules. By combining detection, correction, and registration functions into a unified system, the patent achieves comprehensive protection without the area overhead of separate protection circuits for each module.
Data Source
AI summary
A field programmable gate array (FPGA) with an automatic error detection and correction function for programmable logic modules includes an error checking and correction device. A check code generation circuit in the error checking and correction device performs error correcting code (ECC) encoding according to input data of corresponding programmable logic registers to generate a check code, and refreshes and writes the check code into a check code register according to a clock signal. A check circuit checks outputs of the programmable logic registers and check code registers to generate syndromes for implementing checking. A decoding circuit generates upset signals corresponding to the syndromes according to a trigger enable pulse of a trigger circuit to control a fault register to directly and asynchronously upset content to correct the error. A circuit area is greatly reduced by using the FPGA, thereby improving a degree of integration of the circuit.