FPGA Edge Module for High-Speed Data Transmission
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Solution Overview
Problem
High-performance requirements for computing capability and speed in FPGAs, particularly in AI applications and communication signal processing, necessitate efficient high-speed data transmission.
Innovation Solution
An FPGA with a built-in edge module that connects to multiple resource modules, featuring a read/write controller and cache units, enabling simultaneous read/write operations across multiple resource modules for high-speed data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data transmission uses the winding architecture to connect resource modules, then the FPGA can achieve required user design, but the data transmission speed is limited
Solution Approach 1:
The patent introduces an edge module as an intermediary component between resource modules. The edge module includes a read/write controller and cache units that mediate data transmission between multiple resource modules, enabling simultaneous read/write operations and significantly improving data transmission speed compared to direct winding architecture connections.
Solution Approach 2:
The patent segments the data transmission function by separating read operations and write operations into distinct cache units (read cache units and write cache units). This segmentation allows independent optimization of read and write paths, enabling simultaneous read/write operations without interference and improving overall transmission speed.
2Productivity
If the FPGA implements high-speed data transmission, then computing capability and performance improve, but the implementation cost increases
Solution Approach 1:
The edge module is designed as a universal component that can serve multiple resource modules simultaneously. The read/write controller and cache units can handle read and write operations for multiple different resource modules, making the high-speed transmission capability reusable across the entire FPGA system rather than requiring dedicated high-speed paths for each resource module pair.
Solution Approach 2:
The patent uses cache units as temporary storage copies of data. By creating these intermediate copies in the edge module's cache units, the system can serve multiple read requests from the same data copy without repeatedly accessing the original resource module, thereby improving transmission speed while keeping the implementation cost manageable through shared cache resources.
Data Source
AI summary
An FPGA for implementing data transmission by using a built-in edge module is provided. The FPGA is provided with a built-in edge module. A read port of each resource module connected to the edge module in the FPGA is separately connected to a winding architecture and the edge module, and/or a write port of each resource module connected to the edge module in the FPGA is separately connected to the winding architecture and the edge module. The edge module includes a read/write controller and a cache unit. The read/write controller simultaneously reads data from read ports of a plurality of resource modules and temporarily stores the read data in the cache unit. Alternatively, the read/write controller simultaneously writes temporarily stored data in the cache unit into write ports of the plurality of resource modules.