Configurable FPGA Sockets for Emulation Routing Flexibility

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Solution Overview

Problem

The existing methods for emulating circuit designs using FPGAs are time-consuming, especially when changes are made, as they often require recompiling entire FPGAs due to global routing changes, leading to schedule delays and potential compilation failures.

Innovation Solution

The method involves allocating spare routing resources to FPGA sockets during compilation, allowing for rerouting without recompiling unaffected FPGAs, thereby maintaining optimal emulation speed and reducing the likelihood of compilation failures by using incremental and modular compilation flows, and enabling direct editing through engineering change orders.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If global routing changes are made to accommodate design changes, then routing flexibility is improved, but compilation time increases significantly due to requiring full FPGA recompilation

Engineering Contradiction:

Improverouting flexibilityVSAvoidcompilation time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent segments the FPGA compilation process into modular components: routing resources are separated into dedicated routing sockets that can be independently reconfigured without recompiling the entire FPGA. This allows routing changes to be made in isolation, significantly reducing compilation time while maintaining routing flexibility.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent pre-allocates spare routing resources to routing sockets during the initial compilation phase. These pre-prepared routing resources are immediately available for rapid reconfiguration when design changes occur, eliminating the need for time-consuming full recompilation and enabling fast iterative design changes.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If spare routing resources are pre-allocated to routing sockets, then reconfiguration speed is improved, but resource utilization efficiency deteriorates due to reserved resources

Engineering Contradiction:

Improvereconfiguration speedVSAvoidrouting resource usage

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The patent implements dynamic routing resource management where spare routing resources are pre-allocated to routing sockets for rapid reconfiguration, but these resources can be dynamically released and reallocated based on actual design needs. This dynamic adjustment optimizes both reconfiguration speed and resource utilization efficiency.

Inventive Principle:

Principle #15Dynamics

3Loss of time

If incremental compilation is used for unaffected FPGAs, then compilation time is reduced, but compilation reliability may deteriorate due to partial compilation processes

Engineering Contradiction:

Improvecompilation timeVSAvoidcompilation reliability

Core Design Contradiction:

Loss of timeVSReliability

Solution Approach 1:

The patent introduces routing sockets as intermediary components that mediate between the design changes and the FPGA compilation process. These sockets serve as stable interfaces that can be independently verified and tested, ensuring compilation reliability even when using incremental compilation for unaffected FPGAs.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS9904749B2Configurable FPGA sockets

Publication Date: 2018.02.27 SYNOPSYS INC

AI summary

A method of emulating a circuit design using an emulator is presented. The method includes allocating one or more spare routing resources to one or more field programmable gate array (FPGA) routing sockets when compiling a plurality of FPGAs disposed in the emulator in preparation for emulating the circuit design, and using the one or more spare routing resources to provide one or more routings among the FPGAs in response to one or more changes made to the circuit design.