FPGA Emulator Partitioning for Isolated Debugging
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Solution Overview
Problem
Debugging complex integrated circuits using emulators is time-consuming and resource-intensive due to the need for multiple emulation runs across all hardware resources, which increases complexity and cost.
Innovation Solution
The system partitions the design under test into multiple components, maps each component to a field programmable gate array (FPGA), and uses trace and injection logic to selectively rerun and reemulate specific components, reducing the need for full emulator resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all emulator hardware resources are used for each emulation run to debug complex DUT, then debugging coverage is improved, but debugging time and resource consumption increase significantly
Solution Approach 1:
The patent segments the debugging process by partitioning the design under test into multiple partitions and mapping each partition to a separate FPGA. This allows independent debugging of specific partitions without requiring all emulator resources to be active simultaneously, thereby reducing overall debugging time while maintaining comprehensive debugging coverage through systematic partition-by-partition verification.
2Reliability
If multiple emulation runs are performed to verify complex DUT, then verification completeness is improved, but resource consumption and cost increase
Solution Approach 1:
The design under test is divided into multiple partitions that can be independently mapped to different FPGAs. This segmentation enables verification of complex DUT through multiple targeted runs rather than requiring all resources for each run, reducing overall resource consumption while achieving complete verification coverage across all partitions.
Solution Approach 2:
The patent implements partial action by allowing selective rerunning of only those FPGAs containing partitions that need debugging or verification. Instead of requiring all emulator resources to be active for each verification pass, the system performs partial emulation runs focusing only on relevant partitions, thereby reducing resource consumption while maintaining verification completeness.
3Reliability
If full emulator resources are utilized for each debugging run, then debugging thoroughness is improved, but productivity decreases
Solution Approach 1:
By partitioning the DUT and mapping partitions to separate FPGAs, the system enables parallel or selective debugging of individual partitions. This segmentation allows debugging thoroughness to be maintained through systematic coverage of all partitions while significantly improving productivity by avoiding the need to reconfigure and run all emulator resources for each debugging iteration.
Solution Approach 2:
The system performs partial emulation runs by selectively activating only the FPGAs needed for the current debugging objective. This partial action approach maintains debugging thoroughness by ensuring all partitions are eventually verified while dramatically improving productivity by reducing the scope of each individual emulation run.
Data Source
AI summary
For a design under test (DUT) that is to be emulated, a host system partitions the DUT into multiple partitions and maps each partition to an FPGA of an emulator which will emulate the partition. The host system stores information describing to which FPGAs each component of the DUT has been mapped. Additionally, mapped to each FPGA is trace and injection logic that traces signals exchanged by the FPGA with other FPGAs during emulation of the DUT. After the emulation of the DUT is complete, if a user wishes to debug a component of the DUT, the FPGAs that are configured to emulate the component are identified. For each identified FPGA, the trace and injection logic injects previously traced signals into the logic of the FPGA in order to reemulate the component. The host system generates waveforms for the user that include signals traced during the reemulation of the component.